SUD15N15-95

MOSFET 150V 15A 62W

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SUD15N15-95 Picture
SeekIC No. : 00165013 Detail

SUD15N15-95: MOSFET 150V 15A 62W

floor Price/Ceiling Price

Part Number:
SUD15N15-95
Mfg:
Vishay/Siliconix
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/9/26

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Product Details

Quick Details

Transistor Polarity : N-Channel Drain-Source Breakdown Voltage : 150 V
Gate-Source Breakdown Voltage : +/- 20 V Continuous Drain Current : 15 A
Resistance Drain-Source RDS (on) : 92 mOhms Configuration : Single
Maximum Operating Temperature : + 175 C Mounting Style : SMD/SMT
Package / Case : TO-252-3 Packaging : Reel    

Description

Transistor Polarity : N-Channel
Gate-Source Breakdown Voltage : +/- 20 V
Configuration : Single
Maximum Operating Temperature : + 175 C
Mounting Style : SMD/SMT
Packaging : Reel
Drain-Source Breakdown Voltage : 150 V
Continuous Drain Current : 15 A
Package / Case : TO-252-3
Resistance Drain-Source RDS (on) : 92 mOhms


Specifications

SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions Simulated
Data
Measured
Data
Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 A 2.6 V
On-State Drain Currentb ID(on) VDS =5 V, VGS = 10 V 71 A
Drain-Source On-State Resistanceb rDS(on) VGS = 10V, ID = 15A 0.069 0.077
VGS = 10 V, ID = 15A, TJ = 125°C 0.115
VGS = 10 V, ID = 15A, TJ = 175°C 0.139

VGS = 6V, ID = 10A

0.080 0.081
Forward Voltageb VSD IF= 15A, VGS = 0 V 0.89 0.90 V
Dynamica
Input Capacitance Ciss VGS = 0 V, VDS = 25 V, f = 1 MHz 897 4300 pF
Output Capacitance Coss 126 450
Reverse Transfer Capacitance Crss 73 175
Total Gate Chargec Qg VDS =75 V, VGS = 10 V, ID =15A 21 65 nC
Gate-Source Chargec Qgs 5.5 25
Gate-Drain Chargec Qgd 7 19
Turn-On Delay Timec td(on) VDD = 75V, RL = 5
ID15A, VGEN = 10 V, RG = 2.5
12 15 ns
Rise Timec tr 19 12
Turn-Off Delay Timec td(off) 36 30
Fall Timec tf 41 10
Source-Drain Reverse Recovery Time trr IF = 15A, di/dt = 100 A/µs 48 125





Description

The attached spice model of SUD15N15-95 describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance of SUD15N15-95 is best fit at the gate bias near the threshold voltage.

A novel gate-to-drain feedback capacitance network of SUD15N15-95 is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the SUD15N15-95.



SUD15N15-95 N-Channel 150-V (D-S) 175C MOSFET




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