MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:n/a D/C:09+
SN75LVDS32PWG4, SN75LVDS386, SN75LVDS386DGGR G4 Datasheet download
Category: Integrated Circuits (ICs)
MFG: Texas Instruments
Package Cooled: n/a
D/C: 09+
Description: SN75LVDS32PWG4
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PDF/DataSheet Download
Datasheet: SN7000
File Size: 81454 KB
Manufacturer: SIEMENS [Siemens Semiconductor Group]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: SN75LVDS386
File Size: 318263 KB
Manufacturer: TI [Texas Instruments]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: SN7000
File Size: 81454 KB
Manufacturer: SIEMENS [Siemens Semiconductor Group]
Download : Click here to Download
| Technical/Catalog Information | SN75LVDS32PWG4 |
| Vendor | Texas Instruments |
| Category | Integrated Circuits (ICs) |
| Number of Drivers/Receivers | 0/4 |
| Type | Line Receiver |
| Voltage - Supply | 3 V ~ 3.6 V |
| Package / Case | 16-TSSOP |
| Packaging | Tube |
| Protocol | RS644 |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | SN75LVDS32PWG4 SN75LVDS32PWG4 |
This family of four-, eight-, or sixteen-, differential line receivers (with optional integrated termination) implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Any of the eight or sixteen differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS
nodes. Additionally, the high-speed switching of LVDS signals almost always requires the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT products eliminate this external resistor by integrating it with the receiver.
The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 W. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of receivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, 8- or 16-channel driver, the SN65LVDS389 or SN65LVDS387, over 300 million data transfers per second in single-edge clocked systems are possible with little power. (Note: The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
| UNITS | ||
| VCC(2) Supply voltage range | 0.5 V to 4 V | |
| VI Voltage range: | Enables or Y | 0.5 V to 6 V |
| A or B | 0.5 V to 4 V | |
| IO Output current | ±12 mA | |
| VID| Differential input voltage magnitude | 1 V | |
| Electrostatic discharge: see (3) | SN65' (A, B, and GND) | Class 3, A:15 kV, B: 400 V |
| SN75' (A, B, and GND) | Class 2, A:4 kV, B: 400 V | |
| Continuous power dissipation | See Dissipation Rating Table | |
| Tstg Storage temperature range | 65°C to 150°C | |
| Lead temperature 1,6 mm (1/16 in) from case for 10 seconds |
260°C | |
` Four- ('390), Eight- ('388A), or Sixteen- ('386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
` Integrated 110- Line Termination Resistors on LVDT Products
` Designed for Signaling Rates (1) Up To 630 Mbps
` SN65 Version's Bus-Terminal ESD Exceeds 15 kV
` Operates From a Single 3.3-V Supply
` Typical Propagation Delay Time of 2.6 ns
` Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns
` LVTTL Levels Are 5-V Tolerant
` Open-Circuit Fail Safe
` Flow-Through Pinout
` Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch
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