Features: State-of-the-Art Advanced BiCMOSTechnology (ABT) Design for 3.3-V
Operation and Low-Static PowerDissipation
Members of the Texas InstrumentsWidebusTM Family
Support Mixed-Mode Signal Operation (5-VInput and Output Voltages With 3.3-V VCC)
Support Unregulated Battery OperationDown to 2.7 V
UBT (Universal Bus Transceiver)Combines D-Type Latches and D-TypeFlip-Flops for Operation in Transparent,
Latched, or Clocked Mode
Typical VOLP (Output Ground Bounce)< 0.8 V at VCC = 3.3 V, TA = 25°C
ESD Protection Exceeds 2000 V PerMIL-STD-883, Method 3015; Exceeds 200 VUsing Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mAPer JEDEC Standard JESD-17
Bus Hold on Data Inputs Eliminates theNeed for External Pullup/PulldownResistors
Support Live Insertion
Distributed VCC and GND Pin ConfigurationMinimizes High-Speed Switching Noise
Flow-Through Architecture OptimizesPCB Layout
Package Options Include Plastic 300-milShrink Small-Outline (DL) and Thin ShrinkSmall-Outline (DGG) Packages and
380-milFine-Pitch Ceramic Flat (WD) PackageUsing 25-mil Center-to-Center SpacingsPinout
SpecificationsSupply voltage range, VCC ..................0.5 V to 4.6 V
Input voltage range, VI (see Note 1) ......0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state,
VO (see Note 1) .......................................0.5 V to 7 V
Current into any output in the low state, IO: SN54LVT16500.....96 mA
SN74LVT16500 ..128 mA
Current into any output in the high state,
IO (see Note 2): SN54LVT16500........ ................ 48 mA
SN74LVT16500............64 mA
nput clamp current, IIK (VI < 0) ...........................50 mA
Output clamp current, IOK (VO < 0) .....................50 mA
Maximum power dissipation at TA = 55°C
(in still air) (see Note 3): DGG package.....................1 W
DL package......1.4 W
Storage temperature range, Tstg......65°C to 150°C
DescriptionThe SN74LVT16500 are 18-bit universal bus transceivers designed for low-voltage (3.3-V) VCC operation, but withthe capability to provide a TTL interface to a 5-V system environment.
Data flow in each direction is controlled by output-enable (OEAB and OEBA),latch-enable (LEAB and LEBA),and clock (CLKAB and CLKAB ) inputs. For A-to-B data flow, the device SN74LVT16500 operates in the transparent mode whenLEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB islow, the A-bus data is stored in the latch/flip-flop on the high-to-low transition of CLKAB . Output-enable CLKAB is active high. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are inthe high-impedance state.
SN74LVT16500 Data Sheet
