SN74LVTH16500

Features:

Members of the Texas InstrumentsWidebus^TM Family
State-of-the-Art Advanced BiCMOSTechnology (ABT) Design for 3.3-VOperation and Low Static-PowerDissipation
UBT ^TM (Universal Bus Transceiver)Combines D-Type Latches and D-TypeFlip-Flops for Operation in
Transparent,Latched, or Clocked Mode
Support Mixed-Mode Signal Operation (5-VInput and Output Voltages With 3.3-V V_CC)
Support Unregulated Battery OperationDown to 2.7 V
Typical V_OLP (Output Ground Bounce)< 0.8 V at V_CC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support HotInsertion
Bus Hold on Data Inputs Eliminates theNeed for External Pullup/PulldownResistors
Distributed V_CC and GND Pin ConfigurationMinimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCBLayout
Latch-Up Performance Exceeds 500 mA PerJESD 17
ESD Protection Exceeds 2000 V PerMIL-STD-883, Method 3015; Exceeds 200 VUsing Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic ShrinkSmall-Outline (DL) and Thin ShrinkSmall-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) PackageUsing 25-mil Center-to-Center Spacings 


Pinout




Specifications

Supply voltage range, V_CC  .  . . .. . . .  . . . . 0.5 V to 4.6 V
Input voltage range, V_I (see Note 1)  . .0.5 V to 7 V  
V_oltage range applied to any output in the high-impedance
 or power-off state, V_O (see Note  . . . . 0.5 V to 7 V
V_oltage range applied to any output in the high state,
V_O (see Note 1) .. . . .  . . . . . . . . . . . . .0.5 V to V_CC + 0.5 V
Current into any output in the low state,
I_O: SN54LVTH16500. . . . . . .  . . . .  .. . . .  ... . . . . . . . .  96 mA
      SN74LVTH16500 128 . . . . . . .  .  . .. . . .  . . . . . . . . . . . mA
Current into any output in the high state,
I_O (see Note 2): SN54LVTH16500. . . .  . . . . .. . . . . . . . 48 mA 
                           SN74LVTH16500 . . . .  .. . . . . . . . . . . .64 mA
Input clamp current, IIK (V_I < 0)    . . . . .  . .. . . . . . . . 50 mA
Output clamp current, I_^OK (V_O < 0). . . . .  . . . . . . . . . 50 mA
Output clamp current, I_^OK (V_O < 0)  . . . .  . . .. . . . . . . 50 mA
Package thermal impedance,
JA (see Note 3): DGG package .. . . . . . . . . .. . . . . . . .81°C/W
                              DL package . .  .. . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T_st  .. . . . . . . . .65°C to 150°C
 


Description

The SN74LVTH16500 devices are 18-bit universal bus transceivers designed for low-voltage (3.3-V) V_CC operation,but with the capability to provide a TTL interface to a 5-V system environment.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and OEBA),and clock (CLKAB and OEBA) inputs. For A-to-B data flow, the device SN74LVTH16500 operates in the transparent mode whenLEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB islow, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB . Output-enable OEAB isactive high. When OEAB is high, the Bport outputs are active. When OEAB is low, the B-port outputs are in thehigh-impedance state.