SN74ABT16600

Features:

Members of the Texas Instruments Widebus Family
State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation
UBT  (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent,Latched, Clocked, or Clock-Enabled Mode
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
Flow-Through Architecture Optimizes PCB Layout
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings 


Pinout

Specifications

Supply voltage range, V_CC ..............................................0.5 V to 7 V
nput voltage range, V_I (except I/O ports) (see Note 1)....0.5 V to 7 V
Voltage range applied to any output in
the high or power-off state, _^VO...................................0.5 V to 5.5 V 
Current into any output in the low state, IO: SN54ABT16600 ....96 mA
                                                                        SN74ABT16600..128 mA
Input clamp current, IIK (VI < 0) ..............................................18 mA
Output clamp current, IOK (V_O < 0).............................................50 mA
Package thermal impedance, JA (see Note 2): DGG package   81°C/W
                                                                       DL package ....... 74°C/W
Storage temperature range, T_stg...............................65°C to 150°C


Description

These SN74ABT16600 18-bit universal bus transceivers combineD-type latches and D-type flip-flops to allow dataflow in transparent, latched, clocked, andclock-enabled modes.Data flow in each direction is controlled byoutputenable (OEAB  and OEBA ), latch-enable(LEAB and LEBA), and clock (CLKAB  andCLKENAB) inputs. The clock can be controlled by theclock-enable(CLKENAB and CLKENBA) inputs.For A-to-B data flow, the SN74ABT16600 device operates in thetransparent mode when LEAB is high.WhenLEAB is low, the A data is latched if CLKAB is heldat a high or low logic level. If LEAB is low, theA-bus data isstored in the latch/flip-flop on thehigh-to-low transition of CLKAB . Output enableOEAB is active low. When OEAB is low, theoutputs are active. When OEAB is high, theoutputs are in the high-impedance state.