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SN74LVTH18502APMR, SN74LVTH18502APMR/G4, SN74LVTH18504A

SN74LVTH18502APMR, SN74LVTH18502APMR/G4, SN74LVTH18504A Selling Leads, Datasheet

MFG:Texas Instruments (VA)  Category:Integrated Circuits (ICs)  Package Cooled:QFP  D/C:05++

SN74LVTH18502APMR Picture

SN74LVTH18502APMR, SN74LVTH18502APMR/G4, SN74LVTH18504A Datasheet download

Five Points

Part Number: SN74LVTH18502APMR

Category: Integrated Circuits (ICs)

MFG: Texas Instruments (VA)

Package Cooled: QFP

D/C: 05++

Description: IC 18BIT SCAN TST DEV UBT 64LQFP

 

 
 
 
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About SN74LVTH18502APMR

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Datasheet: SN74LVTH18502APMR

File Size: 628465 KB

Manufacturer: TI [Texas Instruments]

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  • Vendor: Infineon Qty: 63000 Note: SG  Adddate: 2024-11-26
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  • SN7002 E6327

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    Contact: Mr.John Jardine  
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About SN74LVTH18504A

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Datasheet: SN74LVTH18504A

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SN74LVTH18502APMR Parameters

Technical/Catalog InformationSN74LVTH18502APMR
VendorTexas Instruments (VA)
CategoryIntegrated Circuits (ICs)
Logic TypeABT Scan Test Device With Universal Bus Transceivers
Mounting TypeSurface Mount
Package / Case64-LQFP
Supply Voltage2.7 V ~ 3.6 V
PackagingCut Tape (CT)
Operating Temperature-40°C ~ 85°C
Drawing Number296; 4040152; PM; 64
Lead Free StatusLead Free
RoHS StatusRoHS Compliant
Other Names SN74LVTH18502APMR
SN74LVTH18502APMR
296 14932 1 ND
296149321ND
296-14932-1

SN74LVTH18504A General Description

The 'LVTH18504A and 'LVTH182504A scan test devices with 20-bit universal bus transceivers are members of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.

SN74LVTH18504A Maximum Ratings

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 0.5 V to 4.6 V
Input voltage range, VI (see Note 1)  . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . . .  . . . . . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO (see Note 1)   . . . .   . 0.5 V to 7 V
Current into any output in the low state, IO : SN54LVTH18504A. . . . . . . . . .. . .. .. . .. . . . . . . . . . . . . .96 mA
                                                                       SN54LVTH182504A (A port or TDO)   . . . . . . . . . . . . .. .  96 mA
                                                                       SN54LVTH182504A (B port)  . . . . . . . .  . . . . . . .  .  . . . . 30 mA
                                                                       SN74LVTH18504A . . . . . . . . . . . . . . . . . . . . . . . . . .  . . 128 mA 
                                                                       SN74LVTH182504A (A port or TDO)  . . . . . . . . . . . . . .  128 mA
                                                                       SN74LVTH182504A (B port)  . . .. . . . .  . . . . . . . . . . . . .  30 mA
Current into any output in the high state, IO  (see Note 2): SN54LVTH18504A  . . . . . . . . . . . . . . . .  .  48 mA
                                                                                              SN54LVTH182504A (A port or TDO)  . . . .  48 mA
                                                                                              SN54LVTH182504A (B port)  . . . . . . . . . .  30 mA
                                                                                              SN74LVTH18504A . . . . . . . . . . . . . . . .. .. .64 mA  
                                                                                              SN74LVTH182504A (A port or TDO)   . . . .  64 mA
                                                                                              SN74LVTH182504A (B port)  . . . . . . . . . ..  30 mA
Input clamp current, IIK (V< 0)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  50 mA
Output clamp current, IOK (VO < 0)  . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  50 mA
Package thermal impedance, q JA (see Note 3): PM package . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 67°C/W
Storage temperature range, Tstg 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .-65 to 150

SN74LVTH18504A Connection Diagram

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