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SN74LVC543APWG4, SN74LVC543PWR, SN74LVC573

Table of contents:
Info of SN74LVC543APWG4
Info of SN74LVC543PWR
Info of SN74LVC573

SN74LVC543APWG4, SN74LVC543PWR, SN74LVC573 Selling Leads, Datasheet

MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:TSSOP24 D/C:08+

SN74LVC543APWG4, SN74LVC543PWR, SN74LVC573 Picture

SN74LVC543APWG4, SN74LVC543PWR, SN74LVC573 Datasheet download

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Part Number: SN74LVC543APWG4

Category: Integrated Circuits (ICs)

MFG: Texas Instruments

Package Cooled: TSSOP24

D/C: 08+

Description: IC REGISTERED TRANSCVR 24TSSOP

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SN74LVC543APWG4 Parameters

Technical/Catalog Information	SN74LVC543APWG4
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Logic Type	Registered Transceiver, Non-Inverting
Package / Case	24-TSSOP
Packaging	Tube
Mounting Type	Surface Mount
Number of Bits per Element	8
Number of Elements	1 - Single
Operating Temperature	-40°C ~ 85°C
Voltage - Supply	1.65 V ~ 3.6 V
Current - Output High, Low	24mA, 24mA
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	SN74LVC543APWG4 SN74LVC543APWG4

SN74LVC573 General Description

This octal transparent D-type latch is designed for 2.7-V to 3.6-V V_CC operation.

The SN74LVC573 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without the need for interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN74LVC573 is characterized for operation from 40°C to 85°C.

SN74LVC573 Maximum Ratings

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Input voltage range, V_I . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . .0.5 V to 4.6 V
Output voltage range, V_O (see Notes 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to V_CC+ 0.5 V
Input clamp current, I_IK (V_I < 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 50 mA
Output clamp current, I_OK (V_O< 0 or V_O > V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, I_O (V_O= 0 to V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .±50 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ±100mA
Maximum power package dissipation at T_A = 55°C (in still air)(see Note 2):DB package . . . . 0.6 W
                                                                                                                     DW package . . . . 1.6 W
                                                                                                                     PW package . . . . .0.7 W
Operating free-air temperature range, T_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40°C to 85°C
Storage temperature range . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C

SN74LVC573 Features

• EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output VOH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages

SN74LVC573 Connection Diagram

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