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SN74LV373, SN74LV373A, SN74LV373ADBR

Table of contents:
Info of SN74LV373
Info of SN74LV373A
Info of SN74LV373ADBR

SN74LV373, SN74LV373A, SN74LV373ADBR Selling Leads, Datasheet

MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:97 D/C:SSOP

SN74LV373, SN74LV373A, SN74LV373ADBR Datasheet download

Five Points

Part Number: SN74LV373ADBR

Category: Integrated Circuits (ICs)

MFG: Texas Instruments

Package Cooled: 97

D/C: SSOP

Description: IC D-TYPE LATCH OCT 3-ST 20-SSOP

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SN74LV373 General Description

These octal transparent D-type latches are designed for 2.7-V to 5.5-V VCC operation. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN74LV373 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LV373 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74LV373 is characterized for operation from 40°C to 85°C.

SN74LV373 Maximum Ratings

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to V_CC + 0.5 V
Output voltage range, V_O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I< 0 or V_I> V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, I_OK (V_O< 0 or V_O > V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, I_O (V_O = 0 to V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±70 mA
Maximum power dissipation at T_A = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . .0.6 W
DW package . . . . . . . . . . . . . . . . . 1.6 W
PW package . . . . . . . . . . . . . . . . . .0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

SN74LV373 Connection Diagram

SN74LV373A General Description

The 'LV373A devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE ) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down,OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54LV373A is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74LV373A is characterized for operation from 40°C to 85°C.

SN74LV373A Maximum Ratings

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . .−0.5 V to 7 V
Switch I/O voltage range, VIO (see Notes 1 and 2) . . . . . . . .−0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−20 mA
I/O diode current, IIOK (VIO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Switch through current, IT (VIO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . .±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . 73°C/W
                                                     (see Note 3): DB package . . . . . . . . . . . ..82°C/W
                                                     (see Note 3): DGV package . . . . . . . . . . 120°C/W
                                                     (see Note 3): NS package . . . . . . . . . . . . ..64°C/W
                                                     (see Note 3): PW package . . . . . . . . . . ...108°C/W
                                                     (see Note 4): RGY package . . . . . . . . . . . . .39°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . ..−65°C to 150°C

SN74LV373A Connection Diagram

SN74LV373ADBR Parameters

Technical/Catalog Information	SN74LV373ADBR
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Logic Type	D-Type Transparent Latch
Independent Circuits	1
Circuit	8:8
Output Type	Tri-State
Current - Output High, Low	16mA, 16mA
Mounting Type	Surface Mount
Package / Case	20-SSOP
Packaging	Tape & Reel (TR)
Operating Temperature	-40°C ~ 85°C
Delay Time - Propagation	1ns
Voltage - Supply	2 V ~ 5.5 V
Drawing Number	296; 4040065; DB; 14, 16, 20, 24, 28, 30, 38
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	SN74LV373ADBR SN74LV373ADBR 296 14317 2 ND 296143172ND 296-14317-2

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