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SN74LS253NA16, SN74LS256J, SN74LS256N

Table of contents:
Info of SN74LS253NA16
Info of SN74LS256J
Info of SN74LS256N

SN74LS253NA16, SN74LS256J, SN74LS256N Selling Leads, Datasheet

MFG:1662 Package Cooled:CDIP16 D/C:03+

SN74LS253NA16, SN74LS256J, SN74LS256N Picture

SN74LS253NA16, SN74LS256J, SN74LS256N Datasheet download

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Part Number: SN74LS253NA16

MFG: 1662

Package Cooled: CDIP16

D/C: 03+

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SN74LS256J General Description

The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs (A0, A1), an active LOW Enable input (E) and an active LOW Clear input (CL). Each latch has a Data input (D) and four outputs (Q0Q3).

When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs (Q0Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and E are both LOW. When CL is HIGH and E is LOW, the selected output (Q0Q3), determined by the Address inputs, follows D. When the E goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode (E=LOW, CL=HIGH), changing more than one bit of the Address (A0, A1) could impose a transient wrong address. Therefore, this should be done only while in the memory mode (E=CL=HIGH).

SN74LS256J Features

• Serial-to-Parallel Capability
• Output From Each Storage Bit Available
• Random (Addressable) Data Entry
• Easily Expandable
• Active Low Common Clear
• Input Clamp Diodes Limit High Speed Termination Effects

SN74LS256J Connection Diagram

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