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SN74HSTL162822DGGR, SN74HSTL168220GGR, SN74HSTL16918

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Info of SN74HSTL162822DGGR
Info of SN74HSTL168220GGR
Info of SN74HSTL16918

SN74HSTL162822DGGR, SN74HSTL168220GGR, SN74HSTL16918 Selling Leads, Datasheet

MFG:Texas Instruments (VA) Category:Integrated Circuits (ICs) Package Cooled:TSOP D/C:99+

SN74HSTL162822DGGR, SN74HSTL168220GGR, SN74HSTL16918 Datasheet download

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Part Number: SN74HSTL162822DGGR

Category: Integrated Circuits (ICs)

MFG: Texas Instruments (VA)

Package Cooled: TSOP

D/C: 99+

Description: IC MEMORY ADDRESS LATCH 64-TSSOP

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SN74HSTL162822DGGR Parameters

Technical/Catalog Information	SN74HSTL162822DGGR
Vendor	Texas Instruments (VA)
Category	Integrated Circuits (ICs)
Logic Type	D-Type, Addressable
Independent Circuits	1
Circuit	14:28
Output Type	Tri-State
Current - Output High, Low	12mA, 12mA
Mounting Type	Surface Mount
Package / Case	64-TSSOP
Packaging	Cut Tape (CT)
Operating Temperature	-40°C ~ 90°C
Delay Time - Propagation	1.7ns
Voltage - Supply	3.15 V ~ 3.45 V
Drawing Number	296; 4040078; DGG; 48, 56, 64
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	SN74HSTL162822DGGR SN74HSTL162822DGGR 296 9822 1 ND 29698221ND 296-9822-1

SN74HSTL16918 General Description

This 9-bit to 18-bit D-type latch is designed for 3.15-V to 3.45-V VCC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels.

The SN74HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with its own latch-enable (LE) input.

Each of the nine D inputs is tied to the inputs of two D-type latches that provide true data (Q) at the outputs. While LE is low, the Q outputs of the corresponding nine latches follow the D inputs. WhenLE is taken high, the Q outputs are latched at the levels set up at the D inputs.

The SN74HSTL16918 is characterized for operation from 0°C to 70°C.

SN74HSTL16918 Maximum Ratings

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, V_I(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, V_O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, I_IK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, I_OK (V_O< 0 or V_O > V_CC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, I_O (V_O = 0 to V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θ_JA(see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89℃/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65℃ to 150℃
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.

SN74HSTL16918 Features

· Member of the Texas Instruments WidebusE Family
· Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications
· ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
· Latch-Up Performance Exceeds 250 mA Per JESD 17
· Packaged in Plastic Thin Shrink Small-Outline Package

SN74HSTL16918 Connection Diagram

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