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SN74AS373NSR, SN74AS374, SN74AS374BMX

Table of contents:
Info of SN74AS373NSR
Info of SN74AS374
Info of SN74AS374BMX

SN74AS373NSR, SN74AS374, SN74AS374BMX Selling Leads, Datasheet

MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:SOIC-20/5.2mm D/C:00+

SN74AS373NSR, SN74AS374, SN74AS374BMX Datasheet download

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Part Number: SN74AS373NSR

Category: Integrated Circuits (ICs)

MFG: Texas Instruments

Package Cooled: SOIC-20/5.2mm

D/C: 00+

Description: IC LATCH TRANSP OCT D 3ST 20-SOP

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SN74AS373NSR Parameters

Technical/Catalog Information	SN74AS373NSR
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Logic Type	D-Type Transparent Latch
Independent Circuits	1
Circuit	8:8
Output Type	Tri-State
Current - Output High, Low	2.6mA, 24mA
Mounting Type	Surface Mount
Package / Case	20-SOP
Packaging	Tape & Reel (TR)
Operating Temperature	0°C ~ 70°C
Delay Time - Propagation	6ns
Voltage - Supply	4.5 V ~ 5.5 V
Drawing Number	296; 4040062; NS; 14, 16, 20, 24
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	SN74AS373NSR SN74AS373NSR

SN74AS374 General Description

These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relativelylow-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

SN74AS374 Maximum Ratings

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 5.5 V
Package thermal impedance, qJA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.

SN74AS374 Features

· D-Type Flip-Flops in a Single Package With
3-State Bus Driving True Outputs
· Full Parallel Access for Loading
· Buffered Control Inputs
· Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) DIPs

SN74AS374 Connection Diagram

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