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SN74ALVCH16269A, SN74ALVCH16269KR, SN74ALVCH16270

Table of contents:
Info of SN74ALVCH16269A
Info of SN74ALVCH16269KR
Info of SN74ALVCH16270

SN74ALVCH16269A, SN74ALVCH16269KR, SN74ALVCH16270 Selling Leads, Datasheet

MFG:Texas Instruments (VA) Category:Integrated Circuits (ICs) Package Cooled:SSOP D/C:01+

SN74ALVCH16269A, SN74ALVCH16269KR, SN74ALVCH16270 Datasheet download

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Part Number: SN74ALVCH16269KR

Category: Integrated Circuits (ICs)

MFG: Texas Instruments (VA)

Package Cooled: SSOP

D/C: 01+

Description: IC RGSTRD BUS EXCHANGER 56BGA

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SN74ALVCH16269KR Parameters

Technical/Catalog Information	SN74ALVCH16269KR
Vendor	Texas Instruments (VA)
Category	Integrated Circuits (ICs)
Number of Circuits	12 ~ 24-Bit
Package / Case	56-BGA MICROSTAR JUNIOR
Logic Type	Registered Bus Exchanger
Packaging	Cut Tape (CT)
Mounting Type	Surface Mount
Number of Inputs	-
Current - Output High, Low	24mA, 24mA
Supply Voltage	1.65 V ~ 3.6 V
Operating Temperature	-40°C ~ 85°C
Voltage - Supply	1.65 V ~ 3.6 V
Drawing Number	296; 4200583-3; GQL; 56
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	SN74ALVCH16269KR SN74ALVCH16269KR 296 9775 1 ND 29697751ND 296-9775-1

SN74ALVCH16270 General Description

This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus.

The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate CLKEN inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). The control terminals are registered to synchronize the bus-direction changes with CLK.

To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16270 is characterized for operation from 40°C to 85°C.

SN74ALVCH16270 Maximum Ratings

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .0.5 V to 4.6 V
Input voltage range, V_I: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . .  0.5 V to 4.6 V
                                       I/O ports (see Notes 1 and 2) .. . . . . . . . . . . .0.5 V to V_CC + 0.5 V
Output-voltage range, V_O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . .0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Output clamp current, I_OK (V_O< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Continuous output current, I_O . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .±50 mA
Continuous current through each V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±100 mA
Package thermal impedance, _JA(see Note 3): DGG package . . . . . . . . . . . . . . . . . .81°C/W
                                                                          DL package . . . . . . . . . . . . . . . . . . .74°C/W
Storage temperature range, T_stg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C

SN74ALVCH16270 Connection Diagram

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