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QL12X16B, QL12X16B-0C84M/883, QL12X16B0CG84M

Table of contents:
Info of QL12X16B
Info of QL12X16B-0C84M/883
Info of QL12X16B0CG84M

QL12X16B, QL12X16B-0C84M/883, QL12X16B0CG84M Selling Leads, Datasheet

MFG:QUICKLOCOM Package Cooled:QFP D/C:08+/09+

QL12X16B, QL12X16B-0C84M/883, QL12X16B0CG84M Picture

QL12X16B, QL12X16B-0C84M/883, QL12X16B0CG84M Datasheet download

Five Points

Part Number: QL12X16B

MFG: QUICKLOCOM

Package Cooled: QFP

D/C: 08+/09+

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QL12X16B General Description

The QL12x16B is a member of the pASIC 1 Family of very-high-speed CMOS user-programmable ASIC devices. The 192 logic cell fieldprogrammable gate array (FPGA) offers 2,000 usable ASIC gates (4,000 usable PLD gates) of high-performance general-purpose logic in a wide variety of package configurations.

Low-impedance, metal-to-metal, ViaLink interconnect technology provides nonvolatile custom logic capable of operating above 150 MHz. Logic cell delays under 2 ns, combined with input delays of under 1.5 ns and output delays under 3 ns, permit high-density programmable devices to be used with today's fastest microprocessors and DSPs.

Designs can be entered using QuickLogic's QuickWorks Toolkit or most populart third-party CAE tools. QuickWorks combines Verilog/VHDL design entry and simulation tools with device-specific place & route and programming software. Ample on-chip routing channels allow fast, fully automatic place and route of designs using up to 100% of the logic and I/O cells, while maintaining fixed pin-outs.

QL12X16B Maximum Ratings

Supply Voltage ......................... 0.5 to 7.0V
Input Voltage ..................0.5 to VCC +0.5V
ESD Pad Protection ......................... ±2000V
DC Input Current............................. ±20 mA
Latch-up Immunity......................... ±200 mA
Storage Temperature .......65 to + 150
Lead Temperature ...............................300

QL12X16B Features

` Total of 88 I/O pins
   80 Bidirectional Input/Output pins
   6 Dedicated Input/High-Drive pins
   2 Clock/Dedicated input pins with fanout-independent, low-skew clock networks
` Input + logic cell + output delays under 6 ns
` Chip-to-chip operating frequencies up to 110 MHz
` Internal state machine frequencies up to 150 MHz
` Clock skew < 0.5 ns
` Input hysteresis provides high noise immunity
` Built-in scan path permits 100% factory testing of logic and I/O cells and functional testing with Automatic Test Vector Generation (ATVG) software after programming
` Available in 68-pin and 84-pin PLCC, 84-pin CPGA and 100-pin TQFP packages
` 68-pin PLCC compatible with QL8x12B
` 84-pin PLCC compatible with QL16x24B
` 100-pin TQFP compatible with QL8x12B and QL16x24B
` 0.65 CMOS process with ViaLink programming technology

QL12X16B Connection Diagram

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