Features: ` Total of 88 I/O pins 80 Bidirectional Input/Output pins 6 Dedicated Input/High-Drive pins 2 Clock/Dedicated input pins with fanout-independent, low-skew clock networks` Input + logic cell + output delays under 6 ns` Chip-to-chip operating frequencies up to 110 MHz` Internal state ma...
QL12X16B: Features: ` Total of 88 I/O pins 80 Bidirectional Input/Output pins 6 Dedicated Input/High-Drive pins 2 Clock/Dedicated input pins with fanout-independent, low-skew clock networks` Input + logic ...
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The QL12X16B is a member of the pASIC 1 Family of very-high-speed CMOS user-programmable ASIC devices. The 192 logic cell fieldprogrammable gate array (FPGA) offers 2,000 usable ASIC gates (4,000 usable PLD gates) of high-performance general-purpose logic in a wide variety of package configurations.
Low-impedance, metal-to-metal, ViaLink interconnect technology of QL12X16B provides nonvolatile custom logic capable of operating above 150 MHz. Logic cell delays under 2 ns, combined with input delays of under 1.5 ns and output delays under 3 ns, permit high-density programmable devices to be used with today's fastest microprocessors and DSPs.
Designs can be entered using QuickLogic's QuickWorks Toolkit or most populart third-party CAE tools. QuickWorks combines Verilog/VHDL design entry and simulation tools with device-specific place & route and programming software. Ample on-chip routing channels of QL12X16B allow fast, fully automatic place and route of designs using up to 100% of the logic and I/O cells, while maintaining fixed pin-outs.