NB100LVEP17MN, NB100LVEP221, NB100LVEP221FA Selling Leads, Datasheet
MFG:ONS Package Cooled:TQFP52 D/C:2009+
NB100LVEP17MN, NB100LVEP221, NB100LVEP221FA Datasheet download
Part Number: NB100LVEP17MN
MFG: ONS
Package Cooled: TQFP52
D/C: 2009+
MFG:ONS Package Cooled:TQFP52 D/C:2009+
NB100LVEP17MN, NB100LVEP221, NB100LVEP221FA Datasheet download
MFG: ONS
Package Cooled: TQFP52
D/C: 2009+
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Datasheet: NB100ELT23L
File Size: 63876 KB
Manufacturer: ONSEMI [ON Semiconductor]
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PDF/DataSheet Download
Datasheet: NB100LVEP221
File Size: 96506 KB
Manufacturer: ONSEMI [ON Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: NB100LVEP221FA
File Size: 96506 KB
Manufacturer: ONSEMI [ON Semiconductor]
Download : Click here to Download
The NB100LVEP221 is a low skew 1-to-20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential ECL/PECL; CLK1/CLK1 can also receive HSTL signal levels. The LVPECL input signals can be either differential configuration or single-ended (if the VBB output is used).
The LVEP221 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.
To ensure tightest skew, both sides of differential outputs should be terminated identically into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.
The NB100LVEP221, as with most other ECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVEP221 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on PECL terminations, designers should refer to Application Note AND8020/D.
The VBB pin, an internally generated voltage supply, is available to this device only. For single- ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
Single- ended CLK input operation is limited to a VCC . 3.0 V in LVPECL mode, or VEE 3 -3.0 V in NECL mode.
Symbol |
Parameter |
Condition 1 |
Condition 2 |
Rating |
Unit |
VCC |
PECL Mode Power Supply |
GEE = 0 V |
6 |
V | |
VEE |
NECL Mode Power Supply |
GCC = 0 V |
-6 |
V | |
VI |
PECL Mode Input Voltage NECL Mode Input Voltage |
GEE = 0 V GCC = 0 V |
VI VCC VI VEE |
6-6 |
V V |
Iout |
Output Current |
Continuous Surge |
50 100 |
mA mA | |
IBB |
VBB Sink/Source |
±0.5 |
mA | ||
TA |
Operating Temperature Range |
−40 to +85 |
|||
Tstg |
Storage Temperature Range |
−65 to +150 |
|||
JA |
Thermal Resistance (Junction−to−Ambient) JEDEC 51−3 (1S − Single Layer Test Board) |
0 lfpm 500 lfpm |
52 LQFP 52 LQFP |
35.6 30 |
/W /W |
JC |
Thermal Resistance (Junction−to−Ambient) JEDEC 51−6 (2S2P−Multi Layer Test oard) with Filled Thermal Vias |
0 lfpm 500 lfpm | |||
52 LQFP 52 LQFP |
3.2 6.4 |
/W /W | |||
Tsol |
Wave Solder |
<2 to 3 sec @ 248°C |
265 |