Features: • Maximum Input Clock Frequency > 2.5 GHz Typical• Maximum Input Data Rate > 2.5 Gb/s Typical• 525 ps Typical Propagation Delays• Low Profile QFN Package• PECL Mode Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V• NECL Mode Operating Range...
NB100LVEP56: Features: • Maximum Input Clock Frequency > 2.5 GHz Typical• Maximum Input Data Rate > 2.5 Gb/s Typical• 525 ps Typical Propagation Delays• Low Profile QFN Package̶...
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Symbol |
Parameter |
Condition 1 |
Condition 2 |
Rating |
Unit |
VCC |
Positive Mode Power Supply |
VEE = 0 V |
6 |
V | |
VEE |
Negative Mode Power Supply |
VCC = 0 V |
-6 |
V | |
VI |
Positive Mode Input Voltage Negative Mode Input Voltage |
VEE = 0 V VCC = 0 V |
VI VCC VI VEE |
6 -6 |
V V |
Iout |
Output Current |
Continuous Surge |
50 100 |
mA mA | |
IBB |
VBB Sink/Source |
±0.5 |
mA | ||
TA |
Operating Temperature Range |
−40 to +85 |
|||
Tstg |
Storage Temperature Range |
−65 to +150 |
|||
JA |
Thermal Resistance (Junction−to−Ambient) JEDEC 51−3 (1S − Single Layer Test Board) |
0 lfpm 500 lfpm |
TSSOP−20 TSSOP−20 |
140 50 |
/W /W |
JA |
Thermal Resistance (Junction−to−Ambient) JEDEC 51−6 (2S2P−Multi Layer Test oard) with Filled Thermal Vias |
0 lfpm 500 lfpm |
QFN−24 QFN−24 |
37 32 |
/W /W |
JC |
Thermal Resistance (Junction−to−Case) |
Standard Board |
TSSOP−20 QFN−24 |
23 to 41 11 |
/W |
Tsol |
Wave Solder Pb Pb−Free |
<2 to 3 sec @ 248 <2 to 3 sec @ 260 |
265 265 |
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device unctional operation is not implied, damage may occur and reliability may be affected.
The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the NB100LVEP56 ideal for multiplexing low skew clock or differential data signals. The device features both individual and common select inputs to address both data path and random logic applications. Common and individual selects can accept both ECL and CMOS input voltage levels. Multiple VBB pins are provided.
The VBB pin, an internally generated voltage supply, is available to NB100LVEP56 only. For single−ended input operation, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.