LRS1341, LRS1342, LRS1344 Selling Leads, Datasheet
MFG:SHARP Package Cooled:BGA D/C:00+
LRS1341, LRS1342, LRS1344 Datasheet download
Part Number: LRS1341
MFG: SHARP
Package Cooled: BGA
D/C: 00+
LRS1341, LRS1342, LRS1344
- Table of contents:
Info of LRS1341
Info of LRS1342
Info of LRS1344
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About LRS1341
PDF/DataSheet Download
Datasheet: LRS1341
File Size: 202418 KB
Manufacturer: SHARP [Sharp Electrionic Components]
Download : Click here to Download
About LRS1342
PDF/DataSheet Download
Datasheet: LRS1342
File Size: 202418 KB
Manufacturer: SHARP [Sharp Electrionic Components]
Download : Click here to Download
About LRS1302
PDF/DataSheet Download
Datasheet: LRS1302
File Size: 3489088 KB
Manufacturer: SHARP [Sharp Electrionic Components]
Download : Click here to Download
LRS1341 General Description
The LRS1341/LRS1342 is a combination memory organized as 1,048,576 × 16-bit flash memory and 131,072 × 16-bit static RAM in one package.
LRS1341 Maximum Ratings
|
PARAMETER |
SYMBOL |
RATINGS |
UNIT |
NOTES |
|
Supply voltage |
VCC |
-0.2 to +3.9 |
V |
1, 2 |
|
Input voltage |
VIN |
-0.2 to VCC +0.3 |
V |
1, 3, 4 |
|
Operating temperature |
TOPR |
-25 to +85 |
|
|
|
Storage temperature |
TSTG |
-55 to +125 |
|
|
|
F-VPP voltage |
F-VPP |
-0.2 to +14.0 |
V |
1, 4, 5 |
|
F-RP voltage |
F-RP |
-0.5 to +14.0 |
V |
1, 4, 5 |
1. The maximum applicable voltage on any pins with respect to GND.
2. Except F-VPP.
3. Except F-RP.
4. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
5. +14.0 V overshoot is allowed when the pulse width is less than 20 ns.
LRS1341 Features
• Flash Memory and SRAM
• Stacked Die Chip Scale Package
• 72-ball CSP (FBGA072-P-0811) plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
Access time (MAX.): 100 ns
Operating current (MAX.):
The current for F-VCC pin
Read: 25 mA (tCYCLE = 200 ns)
Word write: 17 mA
Block erase: 17 mA
Deep power down current (the current for
F-VCC pin): 10 A (MAX. F-CE F-VCC - 0.2 V,
F-RP -0.2 V, F-VPP 0.2 V)
Optimized array blocking architecture
Two 4K-word boot blocks
Six 4K-word parameter blocks
Thirty-one 32K-word main blocks
Top/Bottom boot location versions
Extended cycling capability
100,000 block erase cycles
Enhanced automated suspend options
Word write suspend to read
Block erase suspend to word write
Block erase suspend to read
• SRAM
Access time (MAX.): 85 ns
Operating current (MAX.):
45 mA
8 mA (tRC, tWC = 1 s)
Standby current: 45 A (MAX.)
Data retention current: 35 A (MAX.)
• Stacked Die Chip Scale Package
• 72-ball CSP (FBGA072-P-0811) plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
Access time (MAX.): 100 ns
Operating current (MAX.):
The current for F-VCC pin
Read: 25 mA (tCYCLE = 200 ns)
Word write: 17 mA
Block erase: 17 mA
Deep power down current (the current for
F-VCC pin): 10 A (MAX. F-CE F-VCC - 0.2 V,
F-RP -0.2 V, F-VPP 0.2 V)
Optimized array blocking architecture
Two 4K-word boot blocks
Six 4K-word parameter blocks
Thirty-one 32K-word main blocks
Top/Bottom boot location versions
Extended cycling capability
100,000 block erase cycles
Enhanced automated suspend options
Word write suspend to read
Block erase suspend to word write
Block erase suspend to read
• SRAM
Access time (MAX.): 85 ns
Operating current (MAX.):
45 mA
8 mA (tRC, tWC = 1 s)
Standby current: 45 A (MAX.)
Data retention current: 35 A (MAX.)
LRS1342 General Description
The LRS1341/LRS1342 is a combination memory organized as 1,048,576 × 16-bit flash memory and 131,072 × 16-bit static RAM in one package.
LRS1342 Maximum Ratings
|
PARAMETER |
SYMBOL |
RATINGS |
UNIT |
NOTES |
|
Supply voltage |
VCC |
-0.2 to +3.9 |
V |
1, 2 |
|
Input voltage |
VIN |
-0.2 to VCC +0.3 |
V |
1, 3, 4 |
|
Operating temperature |
TOPR |
-25 to +85 |
|
|
|
Storage temperature |
TSTG |
-55 to +125 |
|
|
|
F-VPP voltage |
F-VPP |
-0.2 to +14.0 |
V |
1, 4, 5 |
|
F-RP voltage |
F-RP |
-0.5 to +14.0 |
V |
1, 4, 5 |
1. The maximum applicable voltage on any pins with respect to GND.
2. Except F-VPP.
3. Except F-RP.
4. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
5. +14.0 V overshoot is allowed when the pulse width is less than 20 ns.
LRS1342 Features
• Flash Memory and SRAM
• Stacked Die Chip Scale Package
• 72-ball CSP (FBGA072-P-0811) plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
Access time (MAX.): 100 ns
Operating current (MAX.):
The current for F-VCC pin
Read: 25 mA (tCYCLE = 200 ns)
Word write: 17 mA
Block erase: 17 mA
Deep power down current (the current for
F-VCC pin): 10 A (MAX. F-CE F-VCC - 0.2 V,
F-RP -0.2 V, F-VPP 0.2 V)
Optimized array blocking architecture
Two 4K-word boot blocks
Six 4K-word parameter blocks
Thirty-one 32K-word main blocks
Top/Bottom boot location versions
Extended cycling capability
100,000 block erase cycles
Enhanced automated suspend options
Word write suspend to read
Block erase suspend to word write
Block erase suspend to read
• SRAM
Access time (MAX.): 85 ns
Operating current (MAX.):
45 mA
8 mA (tRC, tWC = 1 s)
Standby current: 45 A (MAX.)
Data retention current: 35 A (MAX.)
• Stacked Die Chip Scale Package
• 72-ball CSP (FBGA072-P-0811) plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
Access time (MAX.): 100 ns
Operating current (MAX.):
The current for F-VCC pin
Read: 25 mA (tCYCLE = 200 ns)
Word write: 17 mA
Block erase: 17 mA
Deep power down current (the current for
F-VCC pin): 10 A (MAX. F-CE F-VCC - 0.2 V,
F-RP -0.2 V, F-VPP 0.2 V)
Optimized array blocking architecture
Two 4K-word boot blocks
Six 4K-word parameter blocks
Thirty-one 32K-word main blocks
Top/Bottom boot location versions
Extended cycling capability
100,000 block erase cycles
Enhanced automated suspend options
Word write suspend to read
Block erase suspend to word write
Block erase suspend to read
• SRAM
Access time (MAX.): 85 ns
Operating current (MAX.):
45 mA
8 mA (tRC, tWC = 1 s)
Standby current: 45 A (MAX.)
Data retention current: 35 A (MAX.)
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