LRS1330A, LRS1331, LRS1331C Selling Leads, Datasheet
MFG:SHARP Package Cooled:BGA D/C:00+
LRS1330A, LRS1331, LRS1331C Datasheet download
Part Number: LRS1330A
MFG: SHARP
Package Cooled: BGA
D/C: 00+
LRS1330A, LRS1331, LRS1331C
- Table of contents:
Info of LRS1330A
Info of LRS1331
Info of LRS1331C
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About LRS1302
PDF/DataSheet Download
Datasheet: LRS1302
File Size: 3489088 KB
Manufacturer: SHARP [Sharp Electrionic Components]
Download : Click here to Download
About LRS1331
PDF/DataSheet Download
Datasheet: LRS1331
File Size: 221907 KB
Manufacturer: SHARP [Sharp Electrionic Components]
Download : Click here to Download
About LRS1302
PDF/DataSheet Download
Datasheet: LRS1302
File Size: 3489088 KB
Manufacturer: SHARP [Sharp Electrionic Components]
Download : Click here to Download
LRS1331 General Description
The LRS1331 is a combination memory organized as 1,048,576 × 16-bit flash memory and 262,144 × 16-bit static RAM in one package.
LRS1331 Maximum Ratings
|
PARAMETER |
SYMBOL |
RATINGS |
UNIT |
NOTES |
|
Supply voltage |
VCC |
-0.2 to +3.9 |
V |
1 |
|
Input voltage |
VIN |
-0.2 to VCC +0.3 |
V |
1, 2, 3 |
|
Operating temperature |
TOPR |
-25 to +85 |
| |
|
Storage temperature |
TSTG |
-65 to +125 |
| |
|
F-VCCW voltage |
F-VCCW |
-0.5 to +4.6 |
V |
1, 3, |
1. The maximum applicable voltage on any pins with respect to GND.
2. Except F-VCC, F-VCCW.
3. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
LRS1331 Features
• Flash Memory and SRAM
• Stacked Die Chip Scale Package
• 72-ball 8 mm * 11 mm CSP plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
Access time (MAX.): 90 ns
Operating current (MAX.) (The current for F-VCC pin and F-VCCW pin):
Read: 25 mA (tCYCLE = 200 ns)
Word write: 57 mA
Block erase: 42 mA
Standby current (the current for F-VCC pin): 15 A (MAX. F-RP GND ± 0.2 V)
Optimized array blocking architecture
Two 4K-word boot blocks
Six 4K-word parameter blocks
Thirty-one 32K-word main blocks
Bottom boot location
Extended cycling capability
100,000 block erase cycles
Enhanced automated suspend options
Word write suspend to read
Block erase suspend to word write
Block erase suspend to read
• SRAM
Access time (MAX.): 85 ns
Operating current: 45 mA (MAX.)
Standby current: 15 A (MAX.)
Data retention current: 2 A (MAX.)
• Stacked Die Chip Scale Package
• 72-ball 8 mm * 11 mm CSP plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
Access time (MAX.): 90 ns
Operating current (MAX.) (The current for F-VCC pin and F-VCCW pin):
Read: 25 mA (tCYCLE = 200 ns)
Word write: 57 mA
Block erase: 42 mA
Standby current (the current for F-VCC pin): 15 A (MAX. F-RP GND ± 0.2 V)
Optimized array blocking architecture
Two 4K-word boot blocks
Six 4K-word parameter blocks
Thirty-one 32K-word main blocks
Bottom boot location
Extended cycling capability
100,000 block erase cycles
Enhanced automated suspend options
Word write suspend to read
Block erase suspend to word write
Block erase suspend to read
• SRAM
Access time (MAX.): 85 ns
Operating current: 45 mA (MAX.)
Standby current: 15 A (MAX.)
Data retention current: 2 A (MAX.)
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