75N414S125BC, 75N42102, 75N43102 Selling Leads, Datasheet
MFG:IDT Package Cooled:BGA D/C:0723+
75N414S125BC, 75N42102, 75N43102 Datasheet download
Part Number: 75N414S125BC
MFG: IDT
Package Cooled: BGA
D/C: 0723+
MFG:IDT Package Cooled:BGA D/C:0723+
75N414S125BC, 75N42102, 75N43102 Datasheet download
MFG: IDT
Package Cooled: BGA
D/C: 0723+
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PDF/DataSheet Download
Datasheet: 75N43102
File Size: 43888 KB
Manufacturer: IDT [Integrated Device Technology]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: 75N43102
File Size: 43888 KB
Manufacturer: IDT [Integrated Device Technology]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: 75N43102
File Size: 43888 KB
Manufacturer: IDT [Integrated Device Technology]
Download : Click here to Download
IDT provides proven, industry-leading network search engines (NSEs) that enable and accelerate the intelligent processing of network services in communications equipment. As a part of the complete IDT classification subsystem that includes content inspection engines, the IDT family of NSEs delivers high-performance, feature-rich, easy-to-use, integrated search accelerators.
The IDT 75N42102 NSE is a high performance, low cost, full-ternary 32K x 72 entry device. Each entry location in the NSE has both a Data entry and an associated Mask entry. The NSE devices integrate content addressable memory (CAM) technology with high-performance logic. The device can perform Lookup operations plus Read and Write maintenance operations.
The IDT 75N42102 NSE device has a bi-directional bus that is a multiplexed address and data bus that can support up to 200 million sustained searches per second. This device offers the ability to simultaneously search in mutually exclusive databases substantially increasing the NSE search rate. This device can be configured to enable multiple width lookups from 40 to 288 bits wide. The IDT 75N42102 requires a 1.5-volt VDD1 supply and a 2.5-volt VDD2 supply.
The IDT 75N42102 NSE utilizes the latest high-performance 1.5V CMOS processing technology and is packaged in a JEDEC Standard, thermally enhanced, 304 pin low profile Ball Grid Array.
Full Ternary 32K x 72 bit content addressable memory
Global Mask Registers
40/72/144/288 multiple width lookups
200M sustained lookups per second at 72 and 144 width lookups
Dual bus interface
Cascadable to 8 devices with no glue logic or latency penalty
Glueless interface to standard ZBT™ or Synchronous Pipelined Burst SRAMs
Boundary Scan JTAG Interface (IEEE 1149.1compliant)
1.5V match power supply
2.5V core and I/O power supply