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74HCT166N - 53, 74HCT166P, 74HCT173

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Info of 74HCT166N - 53
Info of 74HCT166P
Info of 74HCT173

74HCT166N - 53, 74HCT166P, 74HCT173 Selling Leads, Datasheet

MFG:TI Package Cooled:DIP D/C:08+/09+

74HCT166N - 53, 74HCT166P, 74HCT173 Picture

74HCT166N - 53, 74HCT166P, 74HCT173 Datasheet download

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Part Number: 74HCT166N - 53

MFG: TI

Package Cooled: DIP

D/C: 08+/09+

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74HCT173 General Description

The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (Q₀ to Q₃) and master reset (MR).

When the two data enable inputs (E₁ and E₂) are LOW, the data on the Dn inputs is loaded into the registersynchronously with the LOW-to-HIGH clock (CP) transition. When one or both E_n inputs are HIGH one set-up time prior to the LOW-to-HIGH clock transition, the register will retain the previous data. Data inputs and clock enable inputs are fully edge-triggered and must be stable only one set-up time prior to the LOW-to-HIGH clock transition.

The master reset input (MR) is an active HIGH asynchronous input. When MR is HIGH, all four flip-flops are reset (cleared) independently of any other input condition. The 3-state output buffers are controlled by a 2-input NOR gate. When both output enable inputs (OE₁ and OE₂) are LOW, the data in the egister is presented to the Qn outputs. When one or both OE_ninputs are HIGH, the outputs are forced to a high impedance OFF-state. The 3-state output buffers are completely independent of the register operation; the OEn transition does not affect the clock and reset operations.

74HCT173 Features

· Gated input enable for hold (do nothing) mode
· Gated output enable control
· Edge-triggered D-type register
· Asynchronous master reset
· Output capability: bus driver
· I_CC category: MSI

74HCT173 Connection Diagram

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