Features: • High Performance 16-bit CPU with 5-Stage Pipeline 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution) 1-Cycle Multiplication (16 * 16 bit), Background Division (32 / 16 bit) in 21 Cycles 1-Cycle Multiply-and-Accumulate (MAC) Instructions Enhanced Boolean...
XC167CI: Features: • High Performance 16-bit CPU with 5-Stage Pipeline 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution) 1-Cycle Multiplication (16 * 16 bit), Background Divis...
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Features: • High Performance 16-bit CPU with 5-Stage Pipeline 25 ns Instruction Cycle Time ...
Parameter |
Symbol |
Limit Values |
Unit |
Unit Notes | |
min. |
max. | ||||
Storage temperature |
TST |
-65 |
150 |
°C |
|
Junction temperature |
TJ |
-40 |
150 |
°C |
under bias |
Voltage on VDDI pins with respect to ground (VSS) |
VDDI |
-0.5 |
3.25 |
V |
|
Voltage on VDDP pins with respect to ground (VSS) |
VDDP |
-0.5 |
6.2 |
V |
|
Voltage on any pin with respect to ground (VSS) |
VIN |
-0.5 |
VDDP + 0.5 |
V |
|
Input current on any pin during overload condition |
-10 |
10 |
mA |
||
Absolute sum of all input currents during overload condition |
|100| |
mA |
The architecture of the XC167 combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way. In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with maximum performance (computing, control, communication).
The XC167 on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resoures as well as external resources (see Figure 3).This bus structure of XC167 enhances the overall system performance by enabling the concurrent operation of several subsystems of the XC167. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the XC167.