XC167CI

Features: • High Performance 16-bit CPU with 5-Stage Pipeline 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution) 1-Cycle Multiplication (16 * 16 bit), Background Division (32 / 16 bit) in 21 Cycles 1-Cycle Multiply-and-Accumulate (MAC) Instructions Enhanced Boolean...

product image

XC167CI Picture
SeekIC No. : 004547697 Detail

XC167CI: Features: • High Performance 16-bit CPU with 5-Stage Pipeline 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution) 1-Cycle Multiplication (16 * 16 bit), Background Divis...

floor Price/Ceiling Price

Part Number:
XC167CI
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/11/23

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

• High Performance 16-bit CPU with 5-Stage Pipeline
   25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
   1-Cycle Multiplication (16 * 16 bit), Background Division (32 / 16 bit) in 21 Cycles
   1-Cycle Multiply-and-Accumulate (MAC) Instructions
   Enhanced Boolean Bit Manipulation Facilities
   Zero-Cycle Jump Execution
   Additional Instructions to Support HLL and Operating Systems
   Register-Based Design with Multiple Variable Register Banks
   Fast Context Switching Support with Two Additional Local Register Banks
   16 Mbytes Total Linear Address Space for Code and Data
   1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
• 16-Priority-Level Interrupt System with 77 Sources, Sample-Rate down to 50 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
• Clock Generation via on-chip PLL (factors 1:0.15 . 1:10), or via Prescaler (factors 1:1 . 60:1)
• On-Chip Memory Modules
   2 Kbytes On-Chip Dual-Port RAM (DPRAM)
   4 Kbytes On-Chip Data SRAM (DSRAM)
   2 Kbytes On-Chip Program/Data SRAM (PSRAM)
   128 Kbytes On-Chip Program Memory (Flash Memory)
• On-Chip Peripheral Modules
   16-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and Conversion Time (down to 2.95 s or 2.55 s)
   Two 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)
   Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6) (3/6 Capture/Compare Channels and 1 Compare Channel)
   Multi-Functional General Purpose Timer Unit with 5 Timers
   Two Synchronous/Asynchronous Serial Channels (USARTs)
   Two High-Speed-Synchronous Serial Channels
   On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects (Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality
   IIC Bus Interface (10-bit addressing, 400 kbit/s) with 3 Channels (multiplexed)
   On-Chip Real Time Clock, Driven by Dedicated Oscillator
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 12 Mbytes External Address Space for Code and Data
   Programmable External Bus Characteristics for Different Address Ranges
   Multiplexed or Demultiplexed External Address/Data Buses
   Selectable Address Bus Width
   16-Bit or 8-Bit Data Bus Width
   Five Programmable Chip-Select Signals
   Hold- and Hold-Acknowledge Bus Arbitration Support
• Up to 103 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
• On-Chip Bootstrap Loader
• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,    Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Debug Support via JTAG Interface
• 144-Pin TQFP Package, 0.5 mm (19.7 mil) pitch



Pinout

  Connection Diagram


Specifications

Parameter
Symbol
Limit Values
Unit
Unit Notes
min.
max.
Storage temperature
TST
-65
150
°C
Junction temperature
TJ
-40
150
°C
under bias
Voltage on VDDI pins with
respect to ground (VSS)
VDDI
-0.5
3.25
V
Voltage on VDDP pins with
respect to ground (VSS)
VDDP
-0.5
6.2
V
Voltage on any pin with
respect to ground (VSS)
VIN
-0.5
VDDP
+ 0.5
V
Input current on any pin
during overload condition
-10
10
mA
Absolute sum of all input
currents during overload
condition
|100|
mA



Description

The architecture of the XC167 combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way. In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with maximum performance (computing, control, communication).

The  XC167  on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data SRAM) and the set of generic peripherals are connected to the CPU via separate buses.

Another bus, the LXBus, connects additional on-chip resoures as well as external resources (see Figure 3).This bus structure of  XC167  enhances the overall system performance by enabling the concurrent operation of several subsystems of the XC167. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the XC167.




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
Cables, Wires
Motors, Solenoids, Driver Boards/Modules
Test Equipment
Undefined Category
Programmers, Development Systems
Power Supplies - Board Mount
View more