Features: • fGPT/2 maximum resolution• 2 independent timers/counters• Timers/counters can be concatenated• 3 operating modes: Timer Mode Gated Timer Mode Counter Mode• Extended capture/reload functions via 16-bit capture/reload register CAPREL• Separate interrup...
XC164-16: Features: • fGPT/2 maximum resolution• 2 independent timers/counters• Timers/counters can be concatenated• 3 operating modes: Timer Mode Gated Timer Mode Counter Mode• ...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Features: • High Performance 16-bit CPU with 5-Stage Pipeline 25 ns Instruction Cycle Time ...
Upon a capture or compare event, the interrupt request flag CCxIR for the respective capture/compare register CCx is automatically set. This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the interrupt enable bit CCxIE. Capture interrupts can be regarded as external interrupt requests with the additional feature of recording the time at which the triggering event occurred.
Each of the CCxIR capture/compare registers has its own bitaddressable interrupt control register and its own interrupt vector allocated. These registers are organized in the same way as all other interrupt control registers. The basic register layout is shown below, Table 17-4 lists the associated addresses