Features: · 3.3V ±0.3V power supply· 1048576 words x 4 banks x 16 bits organization· Self Refresh Current: Standard and Low Power· CAS latency: 2 and 3· Burst Length: 1, 2, 4, 8, and full page· Sequential and Interleave burst· Burst read, single write operation· Byte data controlled by DQM· Power-...
W986416DH: Features: · 3.3V ±0.3V power supply· 1048576 words x 4 banks x 16 bits organization· Self Refresh Current: Standard and Low Power· CAS latency: 2 and 3· Burst Length: 1, 2, 4, 8, and full page· Sequ...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
ITEM | SYMBOL |
RATING |
UNIT |
NOTES |
Input, Output Voltage | VIN,VOUT |
-0.3~ Vcc +0.3 |
V |
1 |
Power Supply Voltage | VCC,VCCQ |
-0.3~4.6 |
V |
1 |
Operating Temperature(-5/-6/-7/- 7L) | TOPR |
0~70 |
°C |
1 |
Operating Temperature(6I) | TOPR |
-40 - 85 |
°C |
1 |
Storage Temperature | TSTG |
-55~150 |
°C |
1 |
Soldering Temperature(10s) | TSOLDER |
260 |
°C |
1 |
Power Dissipation | PD |
1 |
W |
1 |
Short Circuit Output Current | IOUT |
50 |
mA |
1 |
W986416DH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 1M words x 4 banks x 16 bits. Using pipelined architecture and 0.175 mm process technology, W986416DH delivers a data bandwidth of up to 400M bytes per second (-5). For different application, W986416DH is sorted into the following speed grades: -5, -6, -7. The -5 parts can run up to 200 MHz/CL3. The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3. For handheld device application, we also provide a low power option, the grade of -7L, with Self Refresh Current under 400 mA and work well at 2.7V during Self Refresh Mode. For special application, we provide extended temperature option the grade of -6I can work well in wide temperature from -40° C to 85° C.
Accesses to the SDRAM W986416DH are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM W986416DH internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W986416DH is ideal for main memory in high performance applications.