W986408BH

W986408BH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 2M words x 4 banks x 8 bits. Using pipelined architecture and 0.25um process technology, W986408BH delivers a data bandwidth of up to 133M (- 75) bytes per second. To fully comply to the PC133/100/66 personal computer industrial standard, W986408BH is sorted into four speed grades: -75, -8H, -8N, and -10. The 75 is compliant to the PC133/CL3 specification, -8H is compliant to the PC100/CL2 specification, the -8N is compliant to PC100/CL3 specification, and -10 is compliant to PC/66 specification.

Accesses to the W986408BH are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W986408BH is ideal for main memory in high performance applications.