W986416BH

W986416BH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 1M words x 4 banks x 16 bits. Using pipelined architecture and 0.25um process technology, W986416BH delivers a data bandwidth of up to 286M bytes per second (-7). For different application, W986416BH is sorted into four speed grades: -7, -75, -8H, and -8N. The 7 parts can run up to 143Mhz/CL3, the -75 parts are compliant to the PC133/CL3 specification, the -8H parts are compliant to the PC100/CL2 specification, and the -8N is compliant to PC100/CL3 specification.

Accesses to the SDRAM W986416BH are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM W986416BH internal counrter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W986416BH is ideal for main memory in high performance applications.