Features: • Low-power consumption Active: 40mA at 35ns Stand-by: 10 mA (CMOS input/output)2mA CMOS input/output, L version• Single + 2.7 to 3.3V Power Supply• Equal access and cycle time• 35/45/55/70/85/100 ns access time• Easy memory expansion with CE1, CE2 nd OE inp...
V62C3802048L(L): Features: • Low-power consumption Active: 40mA at 35ns Stand-by: 10 mA (CMOS input/output)2mA CMOS input/output, L version• Single + 2.7 to 3.3V Power Supply• Equal access and cycl...
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Features: • Ultra Low-power consumption - Active: 30mA ICC at 70ns - Stand-by: 5 A(CMOS inpu...
Features: • Ultra Low-power consumptionActive: 30mA ICC at 70ns tand-by: 5 mA(CMOS input/out...
Features: • Low-power consumption - Active: 35mA ICC at 70ns - Stand-by: 10 mA (CMOS input/o...
Parameter |
Symbol |
Minimum |
Maximum |
Unit |
Voltage on Any Pin Relative to Gnd |
Vt |
-0.5 |
4.6 |
V |
Power Dissipation |
PT |
- |
1.0 |
W |
Storage Temperature (Plastic) |
Tstg |
-55 |
+150 |
0C |
Temperature Under Bias |
Tbias |
-40 |
+85 |
0C |
The V62C3802048L(L) is a low power CMOS Static RAM organized s 262,144 words by 8 bits. Easy memory expansion is provided y an active LOW CE1, an active HIGH CE2, an active OW OE, and Tri-state I/O's. This device has an automatic ower-down mode feature whendeselected.
Writing to the device is accomplished by taking Chip Enable (CE1) with Write Enable (WE) LOW, and Chip Enable (CE2) HIGH. Readingfrom the device is performed by aking Chip Enable 1 (CE1) with Output Enable (OE) OW while Write Enable (WE ) and Chip Enable 2 (CE2) s HIGH. The I/O pins are placed in a high-impedance state hen the device is deselected: the outputs are disabled during write cycle.
The V62C3802048L(L) comes with a 1V data retention feature nd Lower Standby Power. The V62C3802048L is available in 32-pin 8 x 20 mm TSOP1/8 x 13.4mm STSOP and CSP type 8-fpBGA packages.