V62C1161024L(L)

Features:

• Ultra Low-power consumption
   Active: 30mA ICC at 70ns
   tand-by: 5 mA(CMOS input/output)
                  1 mA(CMOS input/output,Lversion)
• 70/85/100/120 ns access time
• Equal access and cycle time
• Single +1.8V to 2.2V Power Supply
• Tri-state output
• Automatic power-down when deselected
• Multiple center power and ground pins for mproved noise immunity
• Individual byte controls for both Read and rite cycles
• Available in 44 pin TSOP (II) Package


Pinout




Specifications

Parameter	Symbol	Minimum	Maximum	Unit
Voltage on Any Pin Relative to Gnd	Vt	-0.5	+4.0	V
Power Dissipation	PT	-	1.0	W
Storage Temperature (Plastic)	Tstg	-55	+150	0C
Temperature Under Bias	Tbias	-40	+85	0C

Description

The V62C1161024L(L) is a Low Power CMOS Static RAM rganized as 65,536 words by 16 bits. Easy memory expansion s provided by an active LOW (CE) and (OE) pin.

This device has an automatic power-down mode feature hen deselected. Separate Byte Enable controls (BLE
nd BHE) allow individual bytes to be accessed. BLE ontrols the lower bits I/O1 - I/O8. BHE controls the pper bits I/O9 - I/O16.

Writing to these V62C1161024L(L) is performed by taking Chip nable (CE) with Write Enable (WE) and Byte Enable BLE/BHE) LOW.

Reading from the V62C1161024L(L) is performed by taking Chip nable (CE) with Output Enable (OE) and Byte Enable BLE/BHE) LOW while Write Enable (WE) is held IGH.