V62C1162048L(L)

Features:

• Low-power consumption
         - Active: 35mA ICC at 70ns
         - Stand-by: 10 mA (CMOS input/output)
                            2 mA (CMOS input/output, L version)
• 70/85/100/120 ns access time
• Equal access and cycle time
• Single +1.8V to2.2V Power Supply
• Tri-state output
• Automatic power-down when deselected
• Multiple center power and ground pins for improved noise immunity
• Individual byte controls for both Read and Write cycles
• Available in 44 pin TSOPII / 48-fpBGA / 48-mBGA


Pinout




Specifications

Parameter	Symbol	Minimum	Maximum	Unit
Voltage on Any Pin Relative to Gnd	Vt	-0.5	+4.0	V
Power Dissipation	PT	-	1.0	W
Storage Temperature (Plastic)	Tstg	-55	+150	0C
Temperature Under Bias	Tbias	-40	+85	0C

Description

The V62C1162048L(L) is a Low Power CMOS Static RAM organized as 131,072 words by 16 bits. Easy Memory expansion is provided by an active LOW (CE) and (OE) pin.

This device has an automatic power-down mode feature when deselected. Separate Byte Enable controls (BLE and BHE) allow individual bytes to be accessed. BLE controls the lower bits I/O1 - I/O8. BHE controls the pper bits I/O9 - I/O16.

Writing to these V62C1162048L(L) is performed by taking Chip nable (CE) with Write Enable (WE) and Byte Enable BLE/BHE) LOW.

Reading from the V62C1162048L(L) is performed by taking Chip nable (CE) with Output Enable (OE) and Byte Enable BLE/BHE) LOW while Write Enable (WE) is held IGH.