V62C3161024L(L)

Features: • Ultra Low-power consumption - Active: 40mA ICC at 55ns - Stand-by: 5 A (CMOS input/output)1 A (CMOS input/output, L version)• 55/70/85/100 ns access time• Equal access and cycle time• Single +2.7V to 3.3V Power Supply• Tri-state output• Automatic pow...

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SeekIC No. : 004540212 Detail

V62C3161024L(L): Features: • Ultra Low-power consumption - Active: 40mA ICC at 55ns - Stand-by: 5 A (CMOS input/output)1 A (CMOS input/output, L version)• 55/70/85/100 ns access time• Equal access ...

floor Price/Ceiling Price

Part Number:
V62C3161024L(L)
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/3/13

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Product Details

Description



Features:

• Ultra Low-power consumption
  - Active: 40mA ICC at 55ns
  - Stand-by: 5 A (CMOS input/output)
                    1 A (CMOS input/output, L version)
• 55/70/85/100 ns access time
• Equal access and cycle time
• Single +2.7V to 3.3V Power Supply
• Tri-state output
• Automatic power-down when deselected
• Multiple center power and ground pins for improved noise immunity
• Individual byte controls for both Read and Write cycles
• Available in 44 pin TSOP (II) Package



Pinout

  Connection Diagram


Specifications

Parameter
Symbol
Minimum
Maximum
Unit
Voltage on Any Pin Relative to Gnd
Vt
-0.5
+4.6
V
Power Dissipation
PT
-
1.0
W
Storage Temperature (Plastic)
Tstg
-55
+150
Temperature Under Bias
Tbias
-40
+85

* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause
             permanent damage to the device. This is a stress rating only and function operation
            of the device at these or any other conditions outside those indicated in the operational 
            sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions 
            for extended periods may affect reliability.




Description

The V62C3161024L(L) is a Low Power CMOS Static RAM organized as 65,536 words by 16 bits. Easy memory expansion is provided by an active LOW (CE) and (OE) pin.

This device has an automatic power-down mode feature when deselected. Separate Byte Enable controls (BLE and BHE) allow individual bytes to be accessed. BLE controls the lower bits I/O1 - I/O8. BHE controls the upper bits I/O9 - I/O16.

Writing to these devices is performed by taking Chip Enable (CE) with Write Enable (WE) and Byte Enable (BLE/BHE) LOW.

Reading from the device is performed by taking Chip Enable (CE) with Output Enable (OE) and Byte Enable (BLE/BHE) LOW while Write Enable (WE) is held HIGH.




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