Features: • Low-power consumptionActive: 35mA at 55nsStand-by: 10 mA (CMOS input/output)2 mA CMOS input/output, L version• Single +2.2 to 2.7V Power Supply_Typical• Extented Voltage from 2.2 to 3.6V.• Equal access and cycle time• 55/70/85/100 ns access time• Eas...
V62C2802048L(L): Features: • Low-power consumptionActive: 35mA at 55nsStand-by: 10 mA (CMOS input/output)2 mA CMOS input/output, L version• Single +2.2 to 2.7V Power Supply_Typical• Extented Voltag...
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Features: High-speed: 70, 85 ns Ultra low CMOS standby current of 4A (max.) Fully static operation...
Features: High-speed: 70, 85 ns Ultra low standby current of 4A (max.) Fully static operation All ...
Features: • Ultra Low-power consumption -Active: 25mA at 70ns-tand-by: 5 mA (CMOS input/outp...
Parameter |
Symbol |
Minimum |
Maximum |
Unit |
Voltage on Any Pin Relative to Gnd |
Vt |
-0.5 |
3.6 |
V |
Power Dissipation |
PT |
- |
1.0 |
W |
Storage Temperature (Plastic) |
Tstg |
-55 |
+150 |
0C |
Temperature Under Bias |
Tbias |
-40 |
+85 |
0C |
The V62C2802048L(L) is a low power CMOS Static RAM rganized as 262,144 words by 8 bits. Easy memory expansion provided by an active LOW CE1, an active IGH CE2, an active LOW OE, and Tri-state I/O's. This vice has an automatic power-down mode feature when selected.
Writing to the device is accomplished by taking Chip nable 1 (CE1) with Write Enable (WE) LOW, and Chip nable 2 (CE2) HIGH. Reading from the device is performed y taking Chip Enable 1 (CE1) with Output nable (OE) LOW while Write Enable (WE) and Chip nable 2 (CE2) is HIGH. The I/O pins are placed in a igh-impedance state when the device is deselected: the utputs are disabled during a write cycle.
The V62C2802048L(L) comes with a 1V data retention feature nd Lower Standby Power. The V62C2802048L is valable in a 32-pin 8 x 20 mm TSOP1 / STSOP 8x13.4 mm nd CSP type 48-fpBGA packages.