V62C2801024L(L)

The V62C2801024L(L) is a low power CMOS Static RAM organized s 131,072 words by 8 bits. Easy memory expansion is rovided by an active LOW CE1, an active HIGH CE2, an ctive LOW OE, and Tri-state I/O's. This device has an automatic wer-down mode feature when deselected.

Writing to the device is accomplished by taking Chip Enable (CE1) with Write Enable (WE) LOW, and Chip Enable (CE2) HIGH. Reading from the device is performed y taking Chip Enable 1 (CE1) with Output Enable OE) LOW while Write Enable (WE) and Chip Enable 2 CE2) is HIGH. The I/O pins are placed in a high-impedance tate when the device is deselected: the outputs are disabled uring a write cycle.

The V62C2801024L(L) comes with a 1V data retention feature nd Lower Standby Power. The V62C2801024L is available in 32pin 8 x 20 mm TSOP1 / STSOP / 48-fpBGA packages.