V62C2161024L(L)

Features: • Ultra Low-power consumption Active: 35mA ICC at 55ns Stand-by: 5 mA(CMOS input/output)1mA(CMOS input/output,Lversion)• 55/70/85/100 ns access time• Equal access and cycle time• Single +2.2V to 2.7V Power Supply• Tri-state output• Automatic power-down...

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SeekIC No. : 004540204 Detail

V62C2161024L(L): Features: • Ultra Low-power consumption Active: 35mA ICC at 55ns Stand-by: 5 mA(CMOS input/output)1mA(CMOS input/output,Lversion)• 55/70/85/100 ns access time• Equal access and cyc...

floor Price/Ceiling Price

Part Number:
V62C2161024L(L)
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

• Ultra Low-power consumption
   Active: 35mA ICC at 55ns
   Stand-by: 5 mA(CMOS input/output)
                    1 mA(CMOS input/output,Lversion)
• 55/70/85/100 ns access time
• Equal access and cycle time
• Single +2.2V to 2.7V Power Supply
• Tri-state output
• Automatic power-down when deselected
• Multiple center power and ground pins for mproved noise immunity
• Individual byte controls for both Read and rite cycles
• Available in 44 pin TSOP (II) Package



Pinout

  Connection Diagram


Specifications

Parameter
Symbol
Minimum
Maximum
Unit
Voltage on Any Pin Relative to Gnd
Vt
-0.5
+4.6
V
Power Dissipation
PT
-
1.0
W
Storage Temperature (Plastic)
Tstg
-55
+150
0C
Temperature Under Bias
Tbias
-40
+85
0C



Description

The V62C2161024L(L) is a Low Power CMOS Static RAM rganized as 65,536 words by 16 bits. Easy memory expansion s provided by an active LOW (CE) and (OE) pin.

This device has an automatic power-down mode feature hen deselected. Separate Byte Enable controls (BLE nd BHE) allow individual ytes to be accessed. BLEcontrols the lower bits I/O1 - I/O8. BHE controls the uper bits I/O9 - I/O16.

Writing to these devices is performed by taking Chip nable (CE) with Write Enable (WE) and Byte Enable BLE/BHE) LOW.

Reading from the device is performed by taking ChipEnable (CE) with Output Enable (OE) and Byte Enable BLE/BHE) LOW while Write Enable (WE) is heldIGH.




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