Features: • Low-power consumption Active: 25mA at 70ns Stand-by: 10 mA (CMOS input/output)2 mA CMOS input/output, L version• Single + 1.8 to 2.2V Power Supply• Equal access and cycle time• 70/85/100/150 ns access time• Easy memory expansion with CE1, CE2 nd OE inputs&...
V62C1802048L(L): Features: • Low-power consumption Active: 25mA at 70ns Stand-by: 10 mA (CMOS input/output)2 mA CMOS input/output, L version• Single + 1.8 to 2.2V Power Supply• Equal access and cyc...
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Features: • Ultra Low-power consumption - Active: 30mA ICC at 70ns - Stand-by: 5 A(CMOS inpu...
Features: • Ultra Low-power consumptionActive: 30mA ICC at 70ns tand-by: 5 mA(CMOS input/out...
Features: • Low-power consumption - Active: 35mA ICC at 70ns - Stand-by: 10 mA (CMOS input/o...
Parameter |
Symbol |
Minimum |
Maximum |
Unit |
Voltage on Any Pin Relative to Gnd |
Vt |
-0.5 |
4.6 |
V |
Power Dissipation |
PT |
- |
1.0 |
W |
Storage Temperature (Plastic) |
Tstg |
-55 |
+150 |
0C |
Temperature Under Bias |
Tbias |
-40 |
+85 |
0C |
The V62C1802048L(L) is a low power CMOS Static RAM organized s 262,144 words by 8 bits. Easy memory expansion is provided y an active LOW CE1 , an active HIGH CE2, an active L0wOE , and Tri-state I/O's. This device has an automatic ower-down mode feature when deselected.
Writing to the V62C1802048L(L) is accomplished by taking Chip Enable (CE1) with Write Enable (WE) LOW, and Chip Enable (CE2) HIGH. Reading from the device is performed y taking Chip Enable 1 (CE1) with Output Enable OE ) LOW while Write Enable (WE ) and Chip Enable 2 CE2) is HIGH. The I/O pins are placed in a high-impedance tate when the device is deselected: the outputs are isabled during a write cycle.
The V62C1802048L(L) comes with a 1V data retention feature nd Lower Standby Power. The V62C1802048L is available in 32-pin 8 x 13.4 & 8 x 20 mm TSOP1 / STSOP packages.