S3C4510B

Features:

Architecture
` Integrated system for embedded ethernet applications
` Fully 16/32-bit RISC architecture
` Little/Big-Endian mode supported basically, the internal architecture is big-endian. So, the little-endian mode
    only support for external memory.
` Efficient and powerful ARM7TDMI core
` Cost-effective JTAG-based debug solution
` Boundary scan

System Manager
` 8/16/32-bit external bus support for ROM/SRAM, flash memory, DRAM, and external I/O
` One external bus master with bus request/ acknowledge pins
` Support for EDO/normal or SDRAM
` Programmable access cycle (0-7 wait cycles)
` Four-word depth write buffer
` Cost-effective memory-to-peripheral DMA interface

Unified Instruction/Data Cache
` Two-way, set-associative, unified 8K-byte cache
` Support for LRU (least recently used) protocol
` Cache is configurable as an internal SRAM

I²C Serial Interface
` Master mode operation only
` Baud rate generator for serial clock generation

Ethernet Controller
` DMA engine with burst mode
` DMA Tx/Rx buffers (256 bytes Tx, 256 bytes Rx) Rx)
` MAC Tx/Rx FIFO buffers (80 bytes Tx, 16 bytes Rx)
` Data alignment logic
` Endian translation
` 100/10-Mbit per second operation
` Full compliance with IEEE standard 802.3
` MII and 7-wire 10-Mbps interface
` Station management signaling
` On-chip CAM (up to 21 destination addresses)
` Full-duplex mode with PAUSE feature
` Long/short packet modes
` PAD generation

HDLCs
` HDLC protocol features:
  - Flag detection and synchronization
  - Zero insertion and deletion
  - Idle detection and transmission
  - FCS generation and detection (16-bit)
  - Abort detection and transmission

` Address search mode (expandable to 4 bytes)
` Selectable CRC or No CRC mode
` Automatic CRC generator preset
` Digital PLL block for clock recovery
` Baud rate generator
` NRZ/NRZI/FM/Manchester data formats for Tx/Rx
` Loop-back and auto-echo modes
` Tx/Rx FIFOs have 8-word (8 *32-bit) depth
` Selectable 1-word or 4-word data transfer mode
` Data alignment logic
` Endian translation
` Programmable interrupts
` Modem interface
` Up to 10 Mbps operation
` HDLC frame length based on octets
` 2-channel DMA buffer descriptor for Tx/Rx on each HDLC


Pinout




Specifications

Parameter	Symbol	Rating		Unit
Supply voltage	VDD/VDDA	0.3 to 3.8		V
DC input Voltage	VIN	3.3 V I/O	0.3 to VDD + 0.3	V
		5 V-tolerant	0.3 to 5.5
DC input current	IIN	± 10		mA
Operating temperature	TOPR	0 to 70
Storage temperature	TSTG	40 to 125

Description

Samsung's S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems. An integrated Ethernet controller, the S3C4510B, is designed for use in managed communication hubs and routers.

The S3C4510B is built around an outstanding CPU core: the 16/32-bit ARM7TDMI RISC processor designed by Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general purpose microprocessor macro-cell that was developed for use in application-specific and custom-specific integrated circuits. Its simple, elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive applications.

The S3C4510B offers a configurable 8K-byte unified cache/SRAM and Ethernet controller which reduces total system cost. Most of the on-chip function blocks have been designed using an HDL synthesizer and the S3C4510B has been fully verified in Samsung's state-of-the-art ASIC test environment.

Important peripheral functions of S3C4510B include two HDLC channels with buffer descriptor, two UART channels, 2-channel GDMA, two 32-bit timers, and 18 programmable I/O ports. On-board logic includes an interrupt controller, DRAM/ SDRAM controller, and a controller for ROM/SRAM and flash memory. The System Manager includes an internal
32-bit system bus arbiter and an external memory controller.

The following integrated on-chip S3C4510B functions are described in detail in this user's manual:
  - 8K-byte unified cache/SRAM
  - I²C interface
  - Ethernet controller
  - HDLC
  - GDMA
  - UART
  - Timers
  - Programmable I/O ports
  - Interrupt controller