S3C44B0X

Features:

Architecture
· Integrated system for hand-held devices and general embedded applications.
· 16/32-Bit RISC architecture and powerful instruction set with ARM7TDMI CPU core.
· Thumb de-compressor maximizes code density while maintaining performance.
· On-chip ICEbreaker debug support with JTAGbased debugging solution.
· 32x8 bit hardware multiplier.
· New bus architecture to implement Low-Power SAMBA II(SAMSUNG's ARM CPU embedded Micro-controller 
    Bus Architecture).

System Manager
· Little/Big endian support.
· Address space: 32Mbytes per each bank. (Total 256Mbyte)
· Supports programmable 8/16/32-bit data bus width for each bank.
· Fixed bank start address and programmable bank size for 7 banks.
· Programmable bank start address and bank size for one bank.
· 8 memory banks.
    - 6 memory banks for ROM, SRAM etc.
    - 2 memory banks for ROM/SRAM/DRAM(Fast Page, EDO, and Synchronous DRAM)
· Fully Programmable access cycles for all memory banks.
· Supports external wait signal to expend the bus cycle.
· Supports self-refresh mode in DRAM/SDRAM for power-down.
· Supports asymmetric/symmetric address of DRAM.

Cache Memory & internal SRAM
· 4-way set associative ID(Unified)-cache with 8Kbyte.
· The 0/4/8 Kbytes internal SRAM using unused cache memory.
· Pseudo LRU(Least Recently Used) Replace Algorithm.
· Write through policy to maintain the coherence between main memory and cache content.
· Write buffer with four depth.
· Request data first fill technique when cache miss occurs.

Clock & Power Manager
· Low power
· The on-chip PLL makes the clock for operating MCU at maximum 66MHz.
· Clock can be fed selectively to each function block by software.
· Power mode: Normal, Slow, Idle and Stop mode. Normal mode: Normal operating mode.
                                                                                 Slow mode: Low frequency clock without PLL
                                                                                 Idle mode: Stop the clock for only CPU
                                                                                 Stop mode: All clocks are stopped
· Wake up by EINT[7:0] or RTC alarm interrupt from Stop mode.

Interrupt Controller
· 30 Interrupt sources ( Watch-dog timer, 6 Timer, 6 UART, 8 External interrupts, 4 DMA , 2 RTC, 1 ADC, 1 IIC, 1 SIO )
· Vectored IRQ interrupt mode to reduce interrupt latency.
· Level/edge mode on the external interrupt sources
· Programmable polarity of edge and level
· Supports FIQ (Fast Interrupt request) for very urgent interrupt request

Timer with PWM (Pulse Width Modulation)
· 5-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation
· Programmable duty cycle, frequency, and polarity
· Dead-zone generation.
· Supports external clock source.

RTC (Real Time Clock)
· Full clock feature: msec, sec, min, hour, day, week, month, year.
· 32.768 KHz operation.
· Alarm interrupt for CPU wake-up.
· Time tick interrupt

General purpose input/output ports
· 8 external interrupt ports
· 71 multiplexed input/output ports

UART
· 2-channel UART with DMA-based or interruptbased operation
· Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive
· Supports H/W handshaking during transmit/receive
· Programmable baud rate
· Supports IrDA 1.0 (115.2kbps)
· Loop back mode for testing
· Each channel have two internal 32-byte FIFO for Rx and Tx.

DMA Controller
· 2 channel general purpose Direct Memory Access controller without CPU intervention.
· 2 channel Bridge DMA (peripheral DMA) controller.
· Support IO to memory, memory to IO, IO to IO with the Bridge DMA which has 6 type's DMA requestor:
    Software, 4 internal function blocks (UART, SIO, Timer, IIS), and External pins.
· Programmable priority order between DMAs (fixed or round-robin mode)
· Burst transfer mode to enhance the transfer rate on the FPDRAM, EDODRAM and SDRAM.
· Supports fly-by mode on the memory to external device and external device to memory transfer mode

A/D Converter
· 8-ch multiplexed ADC.
· Max. 100KSPS/10-bit.

LCD Controller
· Supports color/monochrome/gray LCD panel
· Supports single scan and dual scan displays
· Supports virtual screen function
· System memory is used as display memory
· Dedicated DMA for fetching image data from system memory
· Programmable screen size
· Gray level: 16 gray levels
· 256 Color levels

Watchdog Timer
· 16-bit Watchdog Timer
· Interrupt request or system reset at time-out

IIC-BUS Interface
· 1-ch Multi-Master IIC-Bus with interrupt-based operation.
· Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 Kbit/s in the standard mode or
    up to 400 Kbit/s in the fast mode.

IIS-BUS Interface
· 1-ch IIS-bus for audio interface with DMA-based operation.
· Serial, 8/16bit per channel data transfers
· Supports MSB-justified data format

SIO (Synchronous Serial I/O)
· 1-ch SIO with DMA-based or interrupt -based operation.
· Programmable baud rates.
· Supports serial data transmit/receive operations 8-bit in SIO.

Operating Voltage Range
· Core : 2.5V I/O : 3.0 V to 3.6 V

Operating Frequency
· Up to 66 MHz

Package
· 160 LQFP / 160 FBGA


Pinout




Specifications

Symbol	Parameter	Rating		Unit
VDD	DC Supply Voltage	3.6		V
VIN	DC Input Voltage	3.3 V Input buffer	4.6
VOUT	DC Input Voltage	3.3 V buffer	4.6
Ilatch	Latch-up Current	± 200		mA
TSTG	Storage Temperature	- 40 to 125

Description

SAMSUNG's S3C44B0X 16/32-bit RISC microprocessor is designed to provide a cost-effective and high performance micro-controller solution for hand-held devices and general applications. To reduce total system cost, S3C44B0X also provides the following: 8KB cache, optional internal SRAM, LCD controller, 2-channel UART with handshake, 4- channel DMA, System manager (chip select logic, FP/ EDO/SDRAM controller), 5-channel timers with PWM, I/O ports, RTC, 8 channel 10-bit ADC, IIC-BUS interface, IIS-BUS interface, Sync. SIO interface and PLL for clock.

The S3C44B0X was developed using a ARM7TDMI core, 0.25 um CMOS standard cells, and a memory compiler. Its low-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and power sensitive applications. Also S3C44B0X adopts a new bus architecture, SAMBA II (SAMSUNG ARM CPU embedded Microcontroller Bus Architecture).

An outstanding feature of the S3C44B0X is its CPU core, a 16/32-bit ARM7TDMI RISC processor (66MHz) designed by Advanced RISC Machines, Ltd. The architectural enhancements of ARM7TDMI include the Thumb decompressor, an on-chip ICE breaker debug support, and a 32-bit hardware multiplier.

By providing a complete set of common system peripherals, the S3C44B0X minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip S3C44B0X functions that are described in this document are as follows:
· 2.5V Static ARM7TDMI CPU core with 8KB cache . (SAMBA II bus architecture up to 66MHz)
· External memory controller. (FP/EDO/SDRAM Control, Chip Select logic)
· LCD controller (up to 256 color DSTN) with 1-ch LCD-dedicated DMA.
· 2-ch general DMAs / 2-ch peripheral DMAs with external request pins
· 2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO
· 1-ch multi-master IIC-BUS controller
· 1-ch IIS-BUS controller
· 5-ch PWM timers & 1-ch internal timer
· Watch Dog Timer
· 71 general purpose I/O ports / 8-ch external interrupt source
· Power control: Normal, Slow, Idle, and Stop mode
· 8-ch 10-bit ADC.
· RTC with calendar function.
· On-chip clock generator with PLL.