Features: • Single 3.3V (± 0.3V) power supply• High speed clock cycle time -6: 166MHz<3-3-3>,-7H: 133MHz<2-2-2>, -7: 133MHz<3-3-3>, -8:100MHz<2-2-2>• Fully synchronous operation referenced to clock rising edge• Possible to assert random column access...
IC42S81600: Features: • Single 3.3V (± 0.3V) power supply• High speed clock cycle time -6: 166MHz<3-3-3>,-7H: 133MHz<2-2-2>, -7: 133MHz<3-3-3>, -8:100MHz<2-2-2>• Fully ...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Features: • Clock frequency: 200, 166, 143 MHz• Fully synchronous; all signals referen...
Features: • Drive Strength for low capacitive bus loading• Clock frequency: 200, 166, ...
Features: • Driver Strength for High capacitive bus loading• Clock frequency: 200, 166...
Symbol |
Parameters |
Rating |
Unit |
VDD |
Supply Voltage (with respect to VSS) |
0.5 to +4.6 |
V |
VDDQ |
Supply Voltage for Output (with respect to VSSQ) |
0.5 to +4.6 |
V |
VI |
Input Voltage (with respect to VSS) |
0.5 to VDD+0.5 |
V |
VO |
Output Voltage (with respect to VSSQ) |
1.0 to VDDQ+0.5 |
V |
IO |
Short circuit output current |
50 |
mA |
PD |
Power Dissipation (TA = 25) |
1 |
W |
TOPT |
Operating Temperature Commercial Industrial |
0 to +70 -40 to +85 |
|
TSTG |
Storage Temperature |
65 to +150 |
Notes:
1. Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
The IC42S81600 and IC42S16800 are high-speed 134,217,728-bit synchronous dynamic randomaccess memories, organized as 4,194,304 x 8 x 4 and 2,097,152 x 16 x 4 (word x bit x bank), respectively.
The synchronous DRAMs of the IC42S81600 achieved high-speed data transfer using the pipeline architecture. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOP-2.