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IC42S16101

Features: • Drive Strength for low capacitive bus loading• Clock frequency: 200, 166, 143 MHz• Fully synchronous; all signals referenced to apositive clock edge• Two banks can be operated simultaneously andindependently• Dual internal bank controlled by A11 (bank sele...

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SeekIC No. : 004370375 Detail

IC42S16101: Features: • Drive Strength for low capacitive bus loading• Clock frequency: 200, 166, 143 MHz• Fully synchronous; all signals referenced to apositive clock edge• Two banks ca...

IC42S16101 Data Sheet

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Part Number:
IC42S16101
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Drive Strength for low capacitive bus loading
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11 (bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
(1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto refresh, self refresh
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Byte controlled by LDQM and UDQM
• Package 400mil 50-pin TSOP-2 and 60ball(16M)
VF-BGA
• Pb(lead)-free package is available


Pinout

Connection Diagram


Specifications

Symbol Parameters Rating Unit
VDD MAX Maximum Supply Voltage 1.0 to +4.6 V
VDDQ MAX Maximum Supply Voltage for Output Buffer 1.0 to +4.6 V
VIN Input Voltage 1.0 to +4.6 V
VOUT Output Voltage 1.0 to +4.6 V
PD MAX Allowable Power Dissipation 1 W
ICS Output Shorted Current 50 mA
TOPR Operating Temperature 0 to +70
TSTG Storage Temperature 55 to +150



Description

ICSI's 16Mb Synchronous DRAM IC42S16101 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.




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