IC42S32800

Notes:
1. Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

The IC42S32800 is a high-speed CMOS configured as a quad 2M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK).

Each of the 2M x 32 bit banks is organized as 4096 rows by 512 columns by 32 bits.Read and write accesses start at a selected locations in a programmed sequence.

Accesses begin with the registration of a BankActive command which is then followed by a Read or Write command

The IC42S32800 provides for programmable Read or Write burst lengths of 1,2,4,8,or full page, with a burst termination operation. An auto precharge function may be enable to provide a self-timed row precharge that is initiated at the end of the burst sequence.The refresh functions,either Auto or Self Refresh are easy to use.

By having a programmable mode register,the system can choose the most suitable modes to maximize its performance.

The IC42S32800 are well suited for applications requiring high memory bandwidth.