Am8030

The Serial Communications Control (SCC)(Am8030/Am8530(H)) is a dual- channel, multi-protoool data communications peripheral designed for use with 8- and 16-bit microprocessors. The SCC(Am8030/Am8530(H)) functions as a serial-to-parallel, parallel-to- serial oonverter/controller. The SCC can be software-contigured to satisfy a wide variety of serial communications applications. The device contains a variety of new, sophisticated intemal functions, including on-chip baud rate generators, digital phase-locked loops, and crystal oscillators, which dramatically reduce the need for external logic. The SCC handles asynchronous formats, synchronous byte-oriented protocols, such as lBM@ Bisync, and syn-chronous bit-oriented protocols, such as HDLC and IBM SDLC.

This versatile device supports virtually any serial data transfer application (cassette, diskette, tape drivers, etc). The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The SCC also has facilities for modem controls in both channels. ln applications where these controls are not needed, the modem controls can be used for general-purpose I/O. The SCC is offered in two versions. The Am8030 is directly compatible with the Z8000 and 8086 CPUs. The Am8530(H) is designed for non-multiplexed buses and is easily interlaced with most other CPUs, such as 8080, Z80, 6800, 68000 and MULTIBUS.

The distinctive characteristisc of Am8030/Am8530(H) are two to 2 Mb/s full duplex serlal channels(Each channel has independent oscillator, baud-rate generator, and PLL for clock recovery, dramatically reducing external components.); programmable protocols(NRZI, and FM data encoding supported under program control.); programmable asynchronous modes(5 to 8-bit characters with programmable stop bits, clock, break detect and error conditions.); Z8000 compatible (The Am8030 interfaces directly with the Z8000 CPU bus and to the Z8000 interrupt structure.); programmable synchronous modes(SDLC and HDLC and SDLC loop supported with frame control, zero insertion and deletion, abort, and residue handling. CRC-16 and CCITF generator and checkers.); compatible with non-multiplexed bus(The Am8530(H) interfaces easily to most other CPUs); enhanced version(The Am8530(H) is an enhanced version whose features include 8-MHz operation and an improved Valid Access Recovery Time (tac) specification.).