A43E06161

Low power supply
- VDD: 1.8V
- VDDQ: 1.8V LVCMOS compatible with multiplexed address
Dual banks / Pulse RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock
Deep Power Down Mode
Clock Frequency: 105MHz @ CL=3 (-95)
133MHz @ CL=3 (-75)
Industrial operating temperature range: -40oC to +85oC for -U
Pb-Free type for -F
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
32ms refresh period (2K cycle)
Available in 50-pin TSOP(II) package

Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +2.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +2.6V
Storage Temperature (T_STG) . . . . . . . . . . -55C to +150C
Soldering Temperature X Time (T_SLODER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C X 10sec
Power Dissipation (P_D) . . . . . . . . . . . . . . . . . . . . . . . 0.8W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . .50mA

The A43E06161 is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 X 524,288 words by 16 bits, fabricated with AMIC^,s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.