Digital Circuit

R_S_FLIP_FLOP

Published:2009/6/25 3:17:00 Author:May

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1OR_GATE

Published:2009/6/25 3:17:00 Author:May

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AND_GATE

Published:2009/6/25 3:15:00 Author:May

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OR_GATE___

Published:2009/6/25 3:14:00 Author:May

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LOGIC_PROBE_1

Published:2009/6/25 4:15:00 Author:May

The probe indicates a high or low at 70% and 30% of V+ (5 to 12 V). One section of the voltage comparator (LM393) senses V in over 70% of supply and the second section senses V in under 30%. These two sections direct-drive the appropriate LEDs. The pulse detector is a CMOS oneshot (MC14538) triggered on the rising edge of the LM393 outputs through 1N4148 diodes. With the RC values shown, it triggered reliably at greater than 30 kHz on both sine and square waves.   (View)

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LOGIC_TEST_PROBE_WITH_MEMORY_

Published:2009/6/25 4:13:00 Author:May

There are two switches: a memory disable switch and a pulse polarity switch. Memory disable is a push-button that resets the memory to the low state when depressed. Pulse polarity is a toggle switch that selects whether the probe responds to a high-level or pulse (+5 V) or a low-level or pulse (ground). (Use IC logic of the same type as is being tested).   (View)

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LOGIC_PROBE

Published:2009/6/25 4:12:00 Author:May

Transistors Q1 and Q2 form a buffer, pro-viding the probe with a reasonable input impe-dance. Q3 and Q4 form a level detecting circuit.As the voltage across the base-emitter junction of the Q3 rises above 0.6 V the transistor turns on thus turning on Q4 and lighting the red (high) LED. Q5 and Q6 perform the same function but for the green (low) LED. Q1, Q4, Q5 are all PNP general purpose silicon transistors (BC178 etc). Q2, Q3, Q6 are all PNP general purpose silicon transistors (BC 108 etc.) The threshold low is≤0.8 V, and the threshold high is≥2.4 V.   (View)

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AUDIBLE_TTL_PROBE

Published:2009/6/25 4:11:00 Author:May

When the probe is in contact with a TTL low (0) the probe emits a low note. With a TTL high (1), a high note is emitted. Power is supplied by the circuit under test.   (View)

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100_K_MEGOHM_DC_PROBE

Published:2009/6/25 4:10:00 Author:May

A 741 op amp is used with t00% ac and dc feedback to provide a typical input impedance of 1011 ohm and unity gain. To avoid hum and rf pickup the input leads should be kept as short as possible and the circuit should be mounted in a small grounded case. Output leads may belong since the output impedance of the circuit is a fraction of an ohm. With no input the output level is indeterminate. Including RI in the cir-cuit through lowers the input impedance to 22 M.   (View)

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RF_PROBE_FOR_VOM

Published:2009/6/25 4:09:00 Author:May

This probe makes possible relative measurements of rf voltages to 200 MHz on a 20,000 ohms-per-volt multimeter．Rf voltage must not exceed the breakdown rating of the IN4149-approximately 100 V.   (View)

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CMOS_LOGIC_PROBE

Published:2009/6/25 4:07:00 Author:May

The logic probe can indicate four input states, as follows: floating input-all LEDs off; logic 0 input-D2 switched on (D3 will briefly flash on); logic 1 input-Dl switched on; pulsing input-D3 switched on, or pulsing in the case of a low frequency input signal (one or both of the other indicators will switch on, showing if one input state predominates).   (View)

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INJECTOR_TRACER

Published:2009/6/25 4:06:00 Author:May

The unit has a separate amplifier and oscillator section allowing them to be used sepa-rately if need be. The injector is a multivibrator running at 1 kHz, with R5 and R6 dividing down the output to a suitable level (≈1V). The tracer is a single-stage amplifier that drives the high impedance earpiece. C4 decouples the input.   (View)

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SIGNAL_INJECTOR_TRACER

Published:2009/6/25 4:04:00 Author:May

The injector is a CMOS oscillator with period approximately equal to 1.4 x C1 x R2 seconds. The values are given for 1 kHz opera-tion. Resistors R3 and R4 divide the output to 1 V. Whereas the oscillator employs the gates in their digital mode, the tracer used them in a linear fashion by applying negative feedback from output to input. They are used in much the same way as op amps. The circuit uses positiveground. It offers an advantage at the earphone output because one side of the earphone must be connected to ground via the case. Use of a positive ground allows the phone to be driven by the two N-channel transistors inside the CD4001 which are arranged in parallel and are thus able to handle more current for better volume.   (View)

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LOGIC_PROBE_YIELDS_THREE_DISCRETE_STATES

Published:2009/6/25 4:02:00 Author:May

The circuit uses a dual LED. When power is applied to the probe through the power leads, and the input is touched to a low level or ground, Q1 is cut off. This will cause Q2 to conduct since the base is positive with respect to the emitter. With Q1 cut off and Q2 con-ducting, the greendiode ofthe dual LED will be forward biased, yielding a green output.Touching the probe tip to a high level will cause Q1 and Q2 to complement, and the red diode will be forward biased, yielding a red output from the LED. An alternating signal will cause alternating conduction of the red and green diodes and willyield an indication approxi-mately amber. In this manner, both static and dynamic signals can be traced with the logic probe.   (View)

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PROGRAMMABLE_GATE

Published:2009/6/25 3:10:00 Author:May

This gate converts an AND gate or an OR gate by applying a logic '1' on the function input. The logic design uses 8 two-input NAND gates. The number of gates may be reduced by replacing the 5 NAND gates enclosed by the dotted line with a two-input exclusive-OR, such as the TTL 7486.   (View)

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LIGHT_ACTIVATED_LOGIC_CIRCUITS

Published:2009/6/25 3:04:00 Author:May

These circuits illustrate some of the common logic functions that can be implemented.   (View)

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TONE_ALERT_DECODER

Published:2009/6/25 2:51:00 Author:May

Circuit Notes PLL (U1) is set with R2 to desired tone frequency. LED lights to indicate lock-up of PLL. Reduce signal level (R1) and readJust R2 to assure lock-up. Delay is selected from counter U3 output. Circuits latches (turns on Q1 to allow audio to speaker) when proper frequency/duration signal is received. To reset latch, a positive voltage must be applied briefly to the R input of U4.   (View)

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PICOAMPERE_TO_VOLTAGE_COMVERTER_WITH_GAIN

Published:2009/6/25 2:43:00 Author:May

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HIGH_IMPEDANCE_PRECISION_RECTIFIER_FOR_AC_DC_CONVERTER

Published:2009/6/25 2:18:00 Author:May

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SHIFT_REGISTER

Published:2009/6/25 2:17:00 Author:May

The shift pulse amplitude is less than 15 volts. If a stage is off，the shift pulse will not becoupled to the next stage，If it is on，the diode will conduct and trigger the next stage.Just prior to the shift pulse the anode supply is interrupted to turn off all stages.The stored capacitor charge determines which stages will be triggered，   (View)

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