Z9951, Z9951AA, Z9952 Selling Leads, Datasheet
MFG:CYPRESS Package Cooled:N/A D/C:09+
Z9951, Z9951AA, Z9952 Datasheet download
Part Number: Z9951
MFG: CYPRESS
Package Cooled: N/A
D/C: 09+
MFG:CYPRESS Package Cooled:N/A D/C:09+
Z9951, Z9951AA, Z9952 Datasheet download
MFG: CYPRESS
Package Cooled: N/A
D/C: 09+
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PDF/DataSheet Download
Datasheet: Z9951
File Size: 15383 KB
Manufacturer: CYPRESS
Download : Click here to Download
PDF/DataSheet Download
Datasheet: Z9951AA
File Size: 50397 KB
Manufacturer:
Download : Click here to Download
PDF/DataSheet Download
Datasheet: Z9952
File Size: 15383 KB
Manufacturer: CYPRESS
Download : Click here to Download
Maximum Input Voltage Relative to VSS: ......VSS - 0.3V
Maximum Input Voltage Relative to VDD:......VDD + 0.3V
Storage Temperature:........... -65°C to + 150°C
Operating Temperature:........... -40°C to +85°C
Maximum ESD protection.................. 2KV
Maximum Power Supply:.................. 5.5V
Maximum Input Current:.................±20mA
This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range:
VSS<(Vin or V out)<V DD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
Maximum Input Voltage Relative to VSS: ......VSS - 0.3V
Maximum Input Voltage Relative to VDD:......VDD + 0.3V
Storage Temperature:........... -65°C to + 150°C
Operating Temperature:........... -40°C to +85°C
Maximum ESD protection.................. 2KV
Maximum Power Supply:.................. 5.5V
Maximum Input Current:.................±20mA
This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range:
VSS<(Vin or V out)<V DD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).