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UR5595, UR5596, UR5596 T/R

Table of contents:
Info of UR5595
Info of UR5596
Info of UR5596 T/R

UR5595, UR5596, UR5596 T/R Selling Leads, Datasheet

MFG:UTC Package Cooled:SOP8 D/C:08+

UR5595, UR5596, UR5596 T/R Datasheet download

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Part Number: UR5595

MFG: UTC

Package Cooled: SOP8

D/C: 08+

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UR5595 General Description

The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 (Stub Series Terminated Logic) specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination.

With an independent VSENSE pin, the UR5595 can provide superior load regulation. The UR5595 provides a VREF output as the reference for the application of the chipset and DIMMs.

The output, VTT, is capable of sinking and sourcing current while egulating the output voltage equal to VDDQ/2. The output stage has been designed to maintain excellent load regulation and with fast response time to minimum the transition preventing shoot-through. The UTC UR5595 also incorporates two distinct power rails that separates the analog circuitry (AVIN) from the power output stage (PVIN). This power rail split can be utilized to reduce the internal power dissipation. And this also permits UTC UR5595 to provide a termination solution for DDRII SDRAM.

UR5595 Maximum Ratings

Parameter		Symbol	Rating	Unit
Supply voltage	PV_IN, AV_IN, V_DDQto GND	V_DD	-0.3 ~ +6	V
Supply voltage	AV_INto GND(Note 1)	V_DD	2.2 ~ 5.5	V
Junction Temperature		T_J	+150	°C
Operating temperature		Topr	0 ~ +125	°C
Storage temperature		Tstg	-65 ~ +150	°C

Note: 1.Signified recommend operating range that indicates conditions for which the device is intended to be functional, but does not guarantee specific performance limits.
2.Absolute maximum ratings indicate limits beyond which damage to the device may occur.

UR5595 Features

* Power regulating with driving and sinking capability
* Low output voltage offset
* No external resistors required
* Low external component count
* Linear topology
* Low cost and easy to use
* Thermal shutdown protection

UR5595 Connection Diagram

UR5596 General Description

The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination.

The UTC UR5596 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs. Besides, an active low shutdown (SHDN) pin provides Suspend To RAM (STR) functionality. When SHDN is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current. Regarding the output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ/2. The output stage has been designed to maintain excellent load regulation while preventing shoot through. The UTC UR5596 also incorporates two distinct power rails that separates the analog circuitry from the power output stage. This allows a split rail approach to be utilized to decrease internal power dissipation and permits UTC UR5596 to provide a termination solution for DDRII SDRAM.

UR5596 Maximum Ratings

PARAMETER		SYMBOL	RATINGS	UNIT
Supply Voltage	PV_IN, AV_IN, V_DDQ to GND	V_DD	-0.3 ~ +6	V
Supply Voltage	AV_IN to GND(Note 1)	V_DD	2.2 ~ 5.5	V
Junction Temperature		T_J	+150
Operation Temperature		T_OPR	0 ~ +125
Storage Temperature		T_STG	-40 ~ +150

Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.

UR5596 Features

* Source and sink current
* Low output voltage offset
* No external resistors required
* Linear topology
* Suspend To Ram (STR) functionality
* Low external component count
* Thermal shutdown protection

UR5596 Connection Diagram

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