MFG:BGA Package Cooled:TI D/C:2004+
TMS320C6413ZTZSA500, TMS320C6414, TMS320C6414DGL25 Datasheet download
MFG: BGA
Package Cooled: TI
D/C: 2004+
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Datasheet: TMS0320F2810PBKAEP
File Size: 2134946 KB
Manufacturer: TI [Texas Instruments]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: TMS320C6414
File Size: 1345587 KB
Manufacturer:
Download : Click here to Download
PDF/DataSheet Download
Datasheet: TMS0320F2810PBKAEP
File Size: 2134946 KB
Manufacturer: TI [Texas Instruments]
Download : Click here to Download
The TMS320C64xTM DSPs (including the TMS320C6414 device) are the highest-performance fixed-point DSP generation in the TMS320C6000TM DSP platform. The TMS320C6414 (C6414) device is based on the second-generation high-performance, advanced VelociTITM very-long-instruction-word (VLIW) architecture (VelocTI.2TM) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64xTM is a code-compatible member of the C6000TM DSP platform.
With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6414 device offers cost-effective solutions to high-performance DSP programming challenges. The C6414 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.
The C64xTM DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)- with VelociTI.2TM extensions. The VelociTI.2TM extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTITM architecture. The C6414 can produce two 32-bit multiply-accumulates (MACs) per cycle for a total of 1200 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6414 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000TM DSP platform devices.
The C6414 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes three multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB†), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.
The C6414 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a WindowsTM debugger interface for visibility into source code execution.
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 2.3 V
Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 90
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
` Highest-Performance Fixed-Point Digital Signal Processor (DSP) TMS320C6414
2.5-, 2-, 1.67-ns Instruction Cycle Time
400-, 500-, 600-MHz Clock Rate
Eight 32-Bit Instructions/Cycle
Twenty-Eight Operations/Cycle
3200, 4000, 4800 MIPS
Fully Software-Compatible With C62x
Pin-Compatible With C6415/16 Devices
` VelociTI.2TM Extensions to VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core
Eight Highly Independent Functional Units With VelociTI.2 Extensions:
Six ALUs (32-/40-Bit) Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
Non-Aligned Load-Store Architecture With 64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
` Instruction Set Features
Byte-Addressable (8-, 16-, 32-, 64-Bit Data)
8-Bit Overflow Protection
Saturation
Bit-Field Extract, Set, Clear
Bit-Counting
Normalization
VelociTI.2TM Increased Orthogonality
` L1/L2 Memory Architecture
128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
` Two External Memory Interfaces (EMIFs)
One 64-Bit (EMIFA)
One 16-Bit (EMIFB)
Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
1280M-Byte Total Addressable External Memory Space
` Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
` Host-Port Interface (HPI)
User-Configurable Bus-Width (32-/16-bit)
Access to Entire Memory Map
` Three Multichannel Buffered Serial Ports (McBSPs)
Direct Interface to T1/E1, MVIP, SCSA Framers
ST-Bus-Switching Compatible
Up to 256 Channels Each
AC97-Compatible
Serial Peripheral Interface (SPI) Compatible (Motorola)
` Three 32-Bit General-Purpose Timers
` General-Purpose I/O (GPIO) Pins
Thirteen Dedicated GPIO Pins
Total of Sixteen GPIO Pins
Programmable Interrupt/Event Generation Modes
` Flexible Phase-Locked-Loop (PLL) Clock Generator
` IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
` 532-Pin Ball Grid Array (BGA) Package (GLZ Suffix), 0.8-mm Ball Pitch
` 0.12-m/6-Level Metal Process
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