MFG:Micrel Inc Category:Integrated Circuits (ICs) Package Cooled:SOP D/C:07/08+
SY100S834, SY100S834LZG, SY100S834LZI Datasheet download
Category: Integrated Circuits (ICs)
MFG: Micrel Inc
Package Cooled: SOP
D/C: 07/08+
Description: IC CLOCK GEN 3.3V/5V 16-SOIC
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PDF/DataSheet Download
Datasheet: SY100S834
File Size: 69621 KB
Manufacturer: MICREL [Micrel Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: SY10
File Size: 80720 KB
Manufacturer: SEMTECH [Semtech Corporation]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: SY100S834LZI
File Size: 74614 KB
Manufacturer: MICREL [Micrel Semiconductor]
Download : Click here to Download
The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2,÷4,÷8) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or,if positive power supplies are used, PECL input signal.In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01F capacitor. The VBB output is designed to act as the switching reference for the input of the SY100S834/L under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current.
The Function Select (FSEL) input is used to determine what clock generation chip function is. When FSEL input is LOW, SY100S834/L functions as a divide by 2, by 4 and by 8 clock generation chip. However, if FSEL input is HIGH, it functions as a divide by 1, by 2 and by 4 clock generation chip. This latter feature will increase the clock frequency by two folds.
The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control.An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore,all associated specification limits are referenced to the negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple SY100S834/Ls in a system.
| Technical/Catalog Information | SY100S834LZG |
| Vendor | Micrel Inc |
| Category | Integrated Circuits (ICs) |
| Type | Clock Generator |
| Voltage - Supply | 3 V ~ 3.8 V |
| Number of Outputs | 3 |
| Input | Differential |
| Output | Differential |
| Frequency-Max | - |
| Package / Case | 16-SOIC |
| Packaging | Tube |
| Operating Temperature | -40°C ~ 85°C |
| Drawing Number | * |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | SY100S834LZG SY100S834LZG 576 2012 5 ND 57620125ND 576-2012-5 |
| Technical/Catalog Information | SY100S834LZI |
| Vendor | Micrel Inc |
| Category | Integrated Circuits (ICs) |
| Type | Clock Generator |
| Voltage - Supply | 3 V ~ 3.8 V |
| Number of Outputs | 3 |
| Input | Differential |
| Output | Differential |
| Frequency-Max | - |
| Package / Case | 16-SOIC |
| Packaging | Tube |
| Operating Temperature | -40°C ~ 85°C |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | SY100S834LZI SY100S834LZI |
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