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STPCC0310BTC3, STPCC0390BTC3(MDBTS708BP1), STPCC390BTC3

Table of contents:
Info of STPCC0310BTC3
Info of STPCC0390BTC3(MDBTS708BP1)
Info of STPCC390BTC3

STPCC0310BTC3, STPCC0390BTC3(MDBTS708BP1), STPCC390BTC3 Selling Leads, Datasheet

MFG:ST Package Cooled:09+ D/C:09+

STPCC0310BTC3, STPCC0390BTC3(MDBTS708BP1), STPCC390BTC3 Picture

STPCC0310BTC3, STPCC0390BTC3(MDBTS708BP1), STPCC390BTC3 Datasheet download

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Part Number: STPCC0310BTC3

MFG: ST

Package Cooled: 09+

D/C: 09+

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STPCC0310BTC3 General Description

At the heart of the STPC Consumer-S is an advanced 64-bit processor block, dubbed the 5ST86. The 5ST86 includes a 486 processor core along with a 64-bit SDRAM controller, advanced 64-bit accelerated graphics and video controller, a hig speed PCI local-bus controller and Industry standard PC chip set functions (Interrupt controller, DMA Controller, Interval timer and ISA bus).

The STPC Consumer-S makes use of a tightly coupled Unified Memory Architecture (UMA), where the same memory array is used for CPU main memory and graphics frame-buffer. This means a reduction in total system memory for system performances that are equal to that of a comparable frame buffer and system memory based system, and generally much better, due to the higher memory bandwidth allowed by attaching the graphics engine directly to the 64-bit processor host interface running at the speed of the processor bus rather than the traditional PCI bus.

The 64-bit wide memory array provides the system with 528MB/s peak bandwidth. This allows for higher resolution screens and greater color depth. The 'standard' PC chipset functions (DMA, interrupt controller, timers, power management logic) are integrated together with the x86 processor core; additional functions such as communications ports are accessed by the STPC Consumer- S via internal ISA bus.

The PCI bus is the main data communication link to the STPC Consumer-S chip. The STPC Consumer- S translates appropriate host bus I/O and Memory cycles onto the PCI bus. It also supports generation of Configuration cycles on the PCI bus. The STPC Consumer-S, as a PCI bus agent (host bridge class), fully complies with PCI specification 2.1. The chip-set also implements the PCI mandatory header registers in Type 0 PCI configuration space for easy porting of PCI aware system BIOS. The device contains a PCI arbitration function for three external PCI devices.

The STPC Consumer-S has two functionnal blocks sharing the same balls : The ISA / IPC / IDE block and the Local Bus / IDE block (see Table 3). Any board with the STPC Consumer-S should be built using only one of these two configurations.

At reset, the configuration is done by 'strap options' which initialises the STPC Consumer-S to the right settings. It is a set of pull-up or pull-down resistors on the memory data bus, checked on reset, which auto-configure the STPC Consumer-S.

STPCC0310BTC3 Maximum Ratings

Symbol	Parameter	Value	Units
V_DDx	DC Supply Voltage	-0.3, 4.0	V
V_I, V_O	Digital Input and Output Voltage	-0.3, V_DD + 0.3	V
T_STG	Storage Temperature	-40, +150
T_OPER	Operating Temperature	0, +70
P_TOT	Total Power Dissipation	4.8	W

STPCC0310BTC3 Features

· POWERFUL x86 PROCESSOR
· 64-BIT 66MHz SDRAM UMA CONTROLLER
· VGA & SVGA CRT CONTROLLER
· 2D GRAPHICS ENGINE
· VIDEO INPUT PORT
· VIDEO PIPELINE
- UP-SCALER
- VIDEO COLOR SPACE CONVERTER
- CHROMA & COLOUR KEY SUPPORT
· TV OUTPUT
- 3-LINE FLICKER FILTER
- CCIR 601/656 SCAN CONVERTER
- NTSC / PAL COMPOSITE, RGB, S-VIDEO
· PCI MASTER / SLAVE CONTROLLER
· ISA MASTER / SLAVE CONTROLLER
· INTEGRATED PERIPHERAL CONTROLLER
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
· OPTIONAL 16-BIT LOCAL BUS INTERFACE
· EIDE CONTROLLER
· I C INTERFACE
· POWER MANAGEMENT UNIT
· 3.3V OPERATION

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