SSM1105, SSM1105920E18F3FIW01, SSM1105V Selling Leads, Datasheet
MFG:ST Package Cooled:CRYSTAL D/C:2006
SSM1105, SSM1105920E18F3FIW01, SSM1105V Datasheet download
Part Number: SSM1105
MFG: ST
Package Cooled: CRYSTAL
D/C: 2006
SSM1105, SSM1105920E18F3FIW01, SSM1105V
- Table of contents:
Info of SSM1105
Info of SSM1105920E18F3FIW01
Info of SSM1105V
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About SSM1105
PDF/DataSheet Download
Datasheet: SSM1105
File Size: 84646 KB
Manufacturer: STMicroelectronics
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About SSM01N60
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Datasheet: SSM01N60
File Size: 109472 KB
Manufacturer: ETC [ETC]
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About SSM1105V
PDF/DataSheet Download
Datasheet: SSM1105V
File Size: 84646 KB
Manufacturer: STMICROELECTRONICS [STMicroelectronics]
Download : Click here to Download
SSM1105V General Description
SSM1105V devices bring in-system programmable (ISP) and in-application programmable (IAP) flash memory to LCD monitor, projector and television applications utilizing a scalar IC from either Pixelworks or other similar image processors or micro-controllers (MCU). Figure 3 shows a typical SSM based system with Pixelworks processor.
The SSM1105V devices feature a dual -bank flash architecture, Dual Display Data Channels (DDC), I2C, PWM channels, general purpose I/O, programmable logic, and in-system programming via either JTAG or I2C.
The dual-bank Flash memory architecture supports full concurrent operation permitting IAP in the field, which means that firmware can be remotely updated with little interruption of system operation. During run-time, the secondary Flash memory array is ideal for EEPROM emulation, thus eliminating the need for a separate external EEPROM.
An on-chip, decode PLD provides for flexible address mapping for both memories. Dual 256 byte SRAMs provide buffer storage for the DDC channels, thus removing the burden from the processor.
SSM1105V Features
System solution for use with image processing scalar ICs
For LCD monitors, projectors, and TVs
Compatible with Pixelworks PW11x/PWx64 families (and similar image processors or micro- controllers)
Single integrated package, including:
Dual bank Flash memories
DDC, I2C, and PWM channels
General purpose I/O
Programmable logic
In-System Programming via JTAG
Dual bank Flash memories
Provide concurrent operation
5 Mbit main Flash memory
384 Kbit secondary Flash memory (divided into 10 small sectors)
Programmable Decode PLD for flexible address mapping of both memories
Dual Display Data Channels (DDC)
Supports DDC for both analog RGB and digital DVI video input channels
DDC1/DDC2B VESA standard compliant
256 byte SRAM buffer for each DDC channel
Dual independent I2C channels
Each capable of master or slave operation
Control A/D converters, video decoders, and future devices (tuner, audio, etc.)
Four Pulse Width Modulator (PWM) channels
16-bit resolution for period and for duty cycle
16-bit clock prescalers
Seven I/O ports with 52 I/O pins for Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, and JTAG
3000 gate PLD with 16 macrocells, for creating glue logic, state machines, clock dividers,decoders, chip-selects, inverters; and to prioritize interrupts from DDC, I2C, PWM
In-System Programming (ISP) with JTAG
Program entire chip in 30-40 seconds with no involvement of the processor
Program with low-cost FlashLINK
Content Security: Programmable Security Bit blocks access of device programmers / readers
Zero-Power Technology: memory and PLD blocks automatically switch to stand-by current between input changes
Package and Specifications
100-pin TQFP, 14 x 14mm
90 ns memory access time
VCC Operating Voltage: 2.7V to 3.6V
For LCD monitors, projectors, and TVs
Compatible with Pixelworks PW11x/PWx64 families (and similar image processors or micro- controllers)
Single integrated package, including:
Dual bank Flash memories
DDC, I2C, and PWM channels
General purpose I/O
Programmable logic
In-System Programming via JTAG
Dual bank Flash memories
Provide concurrent operation
5 Mbit main Flash memory
384 Kbit secondary Flash memory (divided into 10 small sectors)
Programmable Decode PLD for flexible address mapping of both memories
Dual Display Data Channels (DDC)
Supports DDC for both analog RGB and digital DVI video input channels
DDC1/DDC2B VESA standard compliant
256 byte SRAM buffer for each DDC channel
Dual independent I2C channels
Each capable of master or slave operation
Control A/D converters, video decoders, and future devices (tuner, audio, etc.)
Four Pulse Width Modulator (PWM) channels
16-bit resolution for period and for duty cycle
16-bit clock prescalers
Seven I/O ports with 52 I/O pins for Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, and JTAG
3000 gate PLD with 16 macrocells, for creating glue logic, state machines, clock dividers,decoders, chip-selects, inverters; and to prioritize interrupts from DDC, I2C, PWM
In-System Programming (ISP) with JTAG
Program entire chip in 30-40 seconds with no involvement of the processor
Program with low-cost FlashLINK
Content Security: Programmable Security Bit blocks access of device programmers / readers
Zero-Power Technology: memory and PLD blocks automatically switch to stand-by current between input changes
Package and Specifications
100-pin TQFP, 14 x 14mm
90 ns memory access time
VCC Operating Voltage: 2.7V to 3.6V
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