S2002A, S2002K, S2004 Selling Leads, Datasheet
MFG:200 Package Cooled:BGA D/C:AMCC
S2002A, S2002K, S2004
- Table of contents:
Info of S2002A
Info of S2002K
Info of S2004
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About S20
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Datasheet: S20
File Size: 49152 KB
Manufacturer: ST
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About S20
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Datasheet: S20
File Size: 49152 KB
Manufacturer: ST
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About S2004
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Datasheet: S2004
File Size: 386701 KB
Manufacturer: Applied Micro Circuits Corporation
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S2004 General Description
The S2004 facilitates high-speed serial transmission of data in a variety of applications including Gigabit Ethernet, Fibre Channel, serial backplanes, and proprietary point to point links. The chip provides four separate transceivers which can be operated individually or locked together for an aggregate data capacity of >4 Gbps.
Each bi-directional channel provides 8B/10B coding/ decoding, parallel to serial and serial to parallel conversion, clock generation/recovery, and framing. The on-chip transmit PLL synthesizes the high-speed clock from a low-speed reference. The on-chip quad receive PLL is used for clock recovery and data retiming on the four independent data inputs. The transmitter and receiver each support differential PECL-compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a 3.3V power supply and dissipates 2.5 watts.
Figure 1 shows the S2004 and S2204 in a Gigabit Ethernet application. Figure 2 combines the S2004 with a crosspoint switch to demonstrate a serial backplane application. Figure 3 is the input/output diagram. Figures 4 and 5 show the transmit and receive block diagrams, respectively.
S2004 Maximum Ratings
|
Parameter |
Min |
Typ |
Max |
Units |
| Storage Temperature |
-65 |
|
150 |
° C |
| Voltage on VDD with Respect to GND |
-0.5 |
|
+5.0 |
V |
| Voltage on any TTL Input Pin |
-0.5 |
|
3.47 |
V |
| Voltage on any PECL Input Pin |
0 |
|
VDD |
V |
| TTL Output Sink Current |
8 |
mA | ||
| TTL Output Source Current |
8 |
mA | ||
| High Speed PECL Output Source Current |
25 |
mA | ||
| ESD Sensitivity1 |
Over 500 V | |||
1. Human body model.
S2004 Features
• Broad operating rate range (.98 - 1.3 GHz)
- 1062 MHz (Fibre Channel)
- 1250 MHz (Gigabit Ethernet) line rates
- 1/2 Rate Operation
• Quad Transmitter with phase-locked loop (PLL) clock synthesis from low speed reference
• Quad Receiver PLL provides clock and data recovery
• Internally series terminated TTL outputs
• On-chip 8B/10B line encoding and decoding for four separate parallel 8-bit channels
• 32-bit parallel TTL interface with internal series terminated outputs
• Low-jitter serial PECL interface
• Individual local loopback control
• JTAG 1149.1 Boundary scan on low speed I/O signals
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 2.5 W power dissipation
• Compact 23mm x 23mm 208 TBGA package
- 1062 MHz (Fibre Channel)
- 1250 MHz (Gigabit Ethernet) line rates
- 1/2 Rate Operation
• Quad Transmitter with phase-locked loop (PLL) clock synthesis from low speed reference
• Quad Receiver PLL provides clock and data recovery
• Internally series terminated TTL outputs
• On-chip 8B/10B line encoding and decoding for four separate parallel 8-bit channels
• 32-bit parallel TTL interface with internal series terminated outputs
• Low-jitter serial PECL interface
• Individual local loopback control
• JTAG 1149.1 Boundary scan on low speed I/O signals
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 2.5 W power dissipation
• Compact 23mm x 23mm 208 TBGA package
S2004 Typical Application
• Ethernet Backbones
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
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