S2001X11, S2002, S200210668 Selling Leads, Datasheet
MFG:Infineon Package Cooled:BGA D/C:08+/09+
S2001X11, S2002, S200210668 Datasheet download
Part Number: S2001X11
MFG: Infineon
Package Cooled: BGA
D/C: 08+/09+
S2001X11, S2002, S200210668
- Table of contents:
Info of S2001X11
Info of S2002
Info of S200210668
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About S20
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Datasheet: S20
File Size: 49152 KB
Manufacturer: ST
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About S2002
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Datasheet: S2002
File Size: 318583 KB
Manufacturer: Applied Micro Circuits Corporation
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About S20
PDF/DataSheet Download
Datasheet: S20
File Size: 49152 KB
Manufacturer: ST
Download : Click here to Download
S2002 General Description
The S2002 facilitates high-speed serial transmission of data in a variety of applications including Gigabit Ethernet, Fibre Channel, serial backplanes, and proprietary point to point links. The chip provides two separate transceivers which are operated individually for a data capacity of >2 Gbps.
Each bi-directional channel provides 8B/10B coding/ decoding, parallel to serial and serial to parallel conversion, clock generation/recovery, and framing. The on-chip transmit PLL synthesizes the high-speed clock from a low-speed reference. The on-chip dual receive PLL is used for clock recovery and data retiming on the two independent data inputs. The transmitter and receiver each support differential PECL-compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a 3.3V power supply and dissipates 1.85 watts.
Figure 1 shows the S2202 and S2002 in a Gigabit Ethernet application. Figure 2 combines the S2002 with a crosspoint switch to demonstrate a serial backplane application. Figure 3 is the input/ output diagram. Figures 4 and 5 show the transmit and receive block diagrams, respectively.
S2002 Maximum Ratings
|
Parameter |
Min |
Typ |
Max |
Units |
|
Storage Temperature |
-65 |
|
150 |
° C |
| Voltage on VDD with Respect to GND |
-0.5 |
|
+5.0 |
V |
| Voltage on any TTL Input Pin |
-0.5 |
|
3.47 |
V |
|
Voltage on any PECL Input Pin |
0 |
|
VDD |
V |
| TTL Output Sink Current |
|
8 |
mA | |
| TTL Output Source Current |
|
8 |
mA | |
| High Speed PECL Output Source Current |
|
|
25 |
mA |
| ESD Sensitivity 1 |
Over 500 V | |||
S2002 Features
• Broad operating rate range (.98 - 1.3 GHz)
- 1062 MHz (Fibre Channel)
- 1250 MHz (Gigabit Ethernet) line rates
- 1/2 Rate Operation
• Dual Transmitter with phase-locked loop (PLL) clock synthesis from low speed reference
• Dual Receiver PLL provides clock and data recovery
• Internally series terminated TTL outputs
• On-chip 8B/10B line encoding and decoding for two separate parallel 8-bit channels
• Dual 8-bit parallel TTL interfaces with internal series terminated outputs
• Low-jitter serial PECL interface
• Individual local loopback control
• JTAG 1149.1 Boundary scan on low speed I/O signals
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 1.85 W power dissipation
• Compact 21mm x 21mm 156 TBGA package
- 1062 MHz (Fibre Channel)
- 1250 MHz (Gigabit Ethernet) line rates
- 1/2 Rate Operation
• Dual Transmitter with phase-locked loop (PLL) clock synthesis from low speed reference
• Dual Receiver PLL provides clock and data recovery
• Internally series terminated TTL outputs
• On-chip 8B/10B line encoding and decoding for two separate parallel 8-bit channels
• Dual 8-bit parallel TTL interfaces with internal series terminated outputs
• Low-jitter serial PECL interface
• Individual local loopback control
• JTAG 1149.1 Boundary scan on low speed I/O signals
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 1.85 W power dissipation
• Compact 21mm x 21mm 156 TBGA package
S2002 Typical Application
• Ethernet Backbones
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
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