PZ3960C7EB, PZ4S08, PZ5032 Selling Leads, Datasheet
MFG:PHILIPS Package Cooled:TQFP2020 D/C:PHILIPS
PZ3960C7EB, PZ4S08, PZ5032 Datasheet download
Part Number: PZ3960C7EB
MFG: PHILIPS
Package Cooled: TQFP2020
D/C: PHILIPS
PZ3960C7EB, PZ4S08, PZ5032
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Info of PZ3960C7EB
Info of PZ4S08
Info of PZ5032
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About PZ3032
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Datasheet: PZ3032
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About PZ5032
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Datasheet: PZ5032
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PZ5032 General Description
The PZ5032 CPLD (Complex Programmable Logic Device) is the first in a family of Fast Zero Power (FZPE) CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 32 macrocell CPLD. With the FZPE design technique, the PZ5032 offers true pin-to-pin speeds of 6ns, while simultaneously delivering power that is less than 75mA at standby without the need for 'turbo bits' or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD 70% lower at 50MHz. These devices are the first TotalCMOSE PLDs, as they use both a CMOS process technology and the patented full CMOS FZPE design technique. For 3V applications, Philips also offers the high speed PZ3032 CPLD that offers these features in a full 3V implementation.
The Philips FZPE CPLDs introduce the new patent-pending XPLAE (eXtended Programmable Logic Array) architecture. The XPLAE architecture combines the best features of both PLA and PALE type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLAE structure in each logic block provides a fast 6ns PALE path with 5 dedicated product terms per output. This PALE path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 8ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.
The PZ5032 CPLDs are supported by industry standard CAE tools (Cadence, Mentor, Synopsys, Synario, Viewlogic, OrCAD), using text (Abel, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses either Minc or Philips Semiconductors-developed tools.
The PZ5032 CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others.
PZ5032 Maximum Ratings
|
SYMBOL |
PARAMETER |
MIN. |
MAX. |
UNIT |
|
VDD |
Supply voltage |
0.5 |
7.0 |
V |
|
VI |
Input voltage |
1.2 |
VDD+0.5 |
V |
|
VOUT |
Output voltage |
0.5 |
VDD+0.5 |
V |
|
IIN |
Input current |
30 |
30 |
mA |
|
IOUT |
Output current |
100 |
100 |
mA |
|
TJ |
Maximum junction temperature |
40 |
150 |
°C |
|
Tstr |
Storage temperature |
65 |
150 |
°C |
PZ5032 Features
• Industry's first TotalCMOSE PLD both CMOS design and process technologies
• Fast Zero Power (FZPE) design technique provides ultra-low power and very high speed
• High speed pin-to-pin delays of 6ns
• Ultra-low static power of less than 75mA
• Dynamic power that is 70% lower at 50MHz than competing devices
• 100% routable with 100% utilization while all pins and all macrocells are fixed
• Deterministic timing model that is extremely simple to use
• 2 clocks with programmable polarity at every macrocell
• Support for complex asynchronous clocking
• Innovative XPLAE architecture combines high speed with extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• PCI compliant
• Advanced 0.5m E2CMOS process
• Security bit prevents unauthorized access
• Design entry and verification using industry standard and Philips CAE tools
• Reprogrammable using industry standard device programmers
• Innovative Control Term structure provides either sum terms or product terms in each logic block for:
Programmable 3-State buffer
Asynchronous macrocell register preset/reset
• Programmable global 3-State pin facilitates 'bed of nails' testing without using logic resources
• Available in both PLCC and TQFP packages
• Available in both Commercial and Industrial grades
• Fast Zero Power (FZPE) design technique provides ultra-low power and very high speed
• High speed pin-to-pin delays of 6ns
• Ultra-low static power of less than 75mA
• Dynamic power that is 70% lower at 50MHz than competing devices
• 100% routable with 100% utilization while all pins and all macrocells are fixed
• Deterministic timing model that is extremely simple to use
• 2 clocks with programmable polarity at every macrocell
• Support for complex asynchronous clocking
• Innovative XPLAE architecture combines high speed with extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• PCI compliant
• Advanced 0.5m E2CMOS process
• Security bit prevents unauthorized access
• Design entry and verification using industry standard and Philips CAE tools
• Reprogrammable using industry standard device programmers
• Innovative Control Term structure provides either sum terms or product terms in each logic block for:
Programmable 3-State buffer
Asynchronous macrocell register preset/reset
• Programmable global 3-State pin facilitates 'bed of nails' testing without using logic resources
• Available in both PLCC and TQFP packages
• Available in both Commercial and Industrial grades
PZ5032 Connection Diagram
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